An efficient FPGA overlay for portable custom instruction set extensions

Koch, Dirk; Beckhoff, Christian; Lemieux, Guy

doi:10.1109/fpl.2013.6645517

Cited by 41 publications

(16 citation statements)

References 16 publications

(19 reference statements)

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“…Note, Java Virtual Machine's byte-code relates to native machine code as the overlay's application binary relates to the configuration bitstream of the overlay that is implemented on the FPGA fabric. Similarly, like bytecode translation to native machine code for achieving better performance, overlay application may be directly translated into configurations of the underlying FPGA architecture [21], [22].…”

Section: A Overlaysmentioning

confidence: 99%

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A Survey on FPGA Virtualization

Vaishnav

Pham

Koch

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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FPGA accelerators are being applied in various types of systems ranging from embedded systems to cloud computing for their high performance and energy efficiency. Given the scale of deployment, there is a need for efficient application development, resource management, and scalable systems, which make FPGA virtualization extremely important. Consequently, FPGA virtualization methods and hardware infrastructures have frequently been proposed in both academia and industry for addressing multi-tenancy execution, multi-FPGA acceleration, flexibility, resource management and security. In this survey, we identify and classify the various techniques and approaches into three main categories: 1) Resource level, 2) Node level, and 3) Multi-node level. In addition, we identify current trends and developments and highlight important future directions for FPGA virtualization which require further work.

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Section: A Overlaysmentioning

confidence: 99%

“…ZUMA [8] reduced implementation cost by mapping overlay LUTs and overlay multiplexers into LUT-configuration of the hosting FPGA fabric. Koch et al [21] improved the implementation cost further by mapping the overlay routing directly onto the underlying FPGA routing fabric.…”

Section: A Overlaysmentioning

confidence: 99%

A Survey on FPGA Virtualization

Vaishnav

Pham

Koch

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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“…One direction of virtualization using overlays is targeting portability across different FPGAs (and FPGA vendors) and has been shown for coarse-grained ALU-based arrays (CGRAs) [4], [5] as well as for fine-grained LUT-based overlays [6] or even hybrid systems [7]. This method of virtualization shares some ideas of a Java virtual machine where the same bytecode can be executed on different hardware targets.…”

Section: A Overlaysmentioning

confidence: 99%

Resource Elastic Virtualization for FPGAs Using OpenCL

Vaishnav

Pham

Koch

et al. 2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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FPGAs are rising in popularity for acceleration in all kinds of systems. However, even in cloud environments, FPGA devices are typically still used exclusively by one application only. To overcome this, and as an approach to manage FPGA resources with OS functionality, this paper introduces the concept of resource elastic virtualization which allows shrinking and growing of accelerators in the spatial domain with the help of partial reconfiguration. With this, we can serve multiple applications simultaneously on the same FPGA and optimize the resource utilization and consequently the overall system performance. We demonstrate how an implementation of resource elasticity can be realized for OpenCL accelerators along with how it can achieve 2.3x better FPGA utilization and 49% better performance on average while simultaneously lowering waiting time for tasks.

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“…The active mode is selected from four possible modes using two parameters. This module or a similar one could be used as part of a partially reconfigurable application-specific instruction set processor [Koch et al 2013]. …”

Section: The Evaluated Designsmentioning

confidence: 99%

Tconmap

Heyse

Farisi

Bruneel

et al. 2015

ACM Trans. Des. Autom. Electron. Syst.

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Parameterised configurations are FPGA configuration bitstreams in which the bits are defined as functions of user-defined parameters. From a parameterised configuration, it is possible to quickly and efficiently derive specialised, regular configuration bitstreams by evaluating these functions. The specialised bitstreams have different properties and functionality depending on the chosen values of the parameters. The most important application of parameterised configurations is the generation of specialised configuration bitstreams for Dynamic Circuit Specialisation, a technique for optimising circuits at runtime using partial reconfiguration of the FPGA.Generating and using parameterised configurations requires a new FPGA tool flow. In this article, we present a new technology mapping algorithm for parameterised designs, called TCONMAP, that can be used to produce parameterised configurations in which both the configuration of the logic blocks and routing is a function of the parameters. In our experiments, we demonstrate that in using TCONMAP, the depth and area of the mapped circuit is close to the minimal depth and area attainable. Both Dynamic Circuit Specialisation and fine-grained modular reconfiguration are extracted by TCONMAP from the HDL description of the design requiring only simple parameter annotations.

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An efficient FPGA overlay for portable custom instruction set extensions

Cited by 41 publications

References 16 publications

A Survey on FPGA Virtualization

A Survey on FPGA Virtualization

Resource Elastic Virtualization for FPGAs Using OpenCL

Tconmap

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