Pipeline gating: speculation control for energy reduction

Manne, Srilatha; Klauser, Artur; Grunwald, Dirk

doi:10.1109/isca.1998.694769

Cited by 228 publications

(263 citation statements)

References 8 publications

Supporting

Mentioning

258

Contrasting

Unclassified

Order By: Relevance

“…Bahar and Manne [5] introduce pipeline balancing which changes the issue width of the processor depending on the issue IPC over a fixed window size. Other papers [6,7] propose shutting down parts of the processor in a similar manner with comparable results.…”

Section: Related Workmentioning

confidence: 79%

Compiler Directed Issue Queue Energy Reduction

Jones

O’Boyle

Abella

et al. 2011

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. The issue logic of a superscalar processor consumes a large amount of static and dynamic energy. Furthermore, its power density makes it a hot-spot requiring expensive cooling systems and additional packaging. This paper presents a novel approach to energy reduction that uses compiler analysis communicated to the hardware, allowing the processor to dynamically resize the issue queue, fitting it to the available ILP without slowing down the critical path. Limiting the entries available reduces the quantity of instructions dispatched, leading to energy savings in the banked issue queue without adversely affecting performance. Compared with a recently proposed hardware scheme, our approach is faster, simpler and saves more energy. A simplistic scheme achieves 31% dynamic and 33% static energy savings in the issue queue with a 7.2% performance loss. Using more sophisticated compiler analysis we then show that the performance loss can be reduced to less than 0.6% with 24% dynamic and 30% static energy savings and an EDD product of 0.96, outperforming two current state-of-the-art hardware approaches.

show abstract

Section: Related Workmentioning

confidence: 79%

Compiler Directed Issue Queue Energy Reduction

Jones

O’Boyle

Abella

et al. 2011

Lecture Notes in Computer Science

View full text Add to dashboard Cite

show abstract

“…So this low instrumentation overhead is very important. This infrastructure can be used to evaluate optimizations for energy consumption or time-dependent power behavior, for example, the impact on power behavior of pipeline gating [13] or dynamic voltage/frequency scaling [6].…”

Section: An Infrastructure For Characterizing Time-dependent Power Bementioning

confidence: 99%

Efficient Program Power Behavior Characterization

Jiménez

Kremer

2007

High Performance Embedded Architectures and Compilers

View full text Add to dashboard Cite

Abstract. Fine-grained program power behavior is useful in both evaluating power optimizations and observing power optimization opportunities. Detailed power simulation is time consuming and often inaccurate. Physical power measurement is faster and objective. However, fine-grained measurement generates enormous amounts of data in which locating important features is difficult, while coarse-grained measurement sacrifices important detail. We present a program power behavior characterization infrastructure that identifies program phases, selects a representative interval of execution for each phase, and instruments the program to enable precise power measurement of these intervals to get their time-dependent power behavior. We show that the representative intervals accurately model the fine-grained time-dependent behavior of the program. They also accurately estimate the total energy of a program. Our compiler infrastructure allows for easy mapping between a measurement result and its corresponding source code. We improve the accuracy of our technique over previous work by using edge vectors, i.e., counts of traversals of control-flow edges, instead of basic block vectors, as well as incorporating event counters into our phase classification. We validate our infrastructure through the physical power measurement of 10 SPEC CPU 2000 integer benchmarks on an Intel Pentium 4 system. We show that using edge vectors reduces the error of estimating total program energy by 35% over using basic block vectors, and using edge vectors plus event counters reduces the error of estimating the fine-grained time-dependent power profile by 22% over using basic block vectors.

show abstract

“…Most existing work [10,11,12] assume that the dynamic throttling can be achieved instantly. However, turning on/off a functional unit in a short time (e.g.…”

Section: Clock Rampingmentioning

confidence: 99%

“…In this case, the clock gating takes a few cycles and can be called clock ramping for differentiation from the conventional clock gating approach in [10]. To avoid the performance penalty introduced by the extra switching cycles, the clock ramping with hard-ware prescan (CRHP) is proposed in [15].…”

Section: Clock Rampingmentioning

confidence: 99%

Power Modeling and Reduction of VLIW Processors

Liao

2003

Compilers and Operating Systems for Low Power

View full text Add to dashboard Cite

In this paper, we first present a cycle-accurate power simulator based on the IMPACT toolset. This simulator allows the designer to evaluate both VLIW compiler and microarchitecture innovations for power reduction. Using this simulator, we then develop and compare the following techniques with a bounded performance loss of 1% compared to the case without any dynamic throttling: (i) clock ramping with hardware-based prescan (CRHP), and (ii) clock ramping with compiler-based prediction (CRCP). Experiments using SPEC2000 floating point benchmarks show that the power consumed by floating point units can be reduced by up to 31% and 37%, in CRHP and CRCP respectively.

show abstract

Pipeline gating: speculation control for energy reduction

Cited by 228 publications

References 8 publications

Compiler Directed Issue Queue Energy Reduction

Compiler Directed Issue Queue Energy Reduction

Efficient Program Power Behavior Characterization

Power Modeling and Reduction of VLIW Processors

Contact Info

Product

Resources

About