Physical design and synthesis (panel)

Bushroe, R. G.; Pedram, Massoud; Camposano, Raúl; Micheli, Giovanni De; Domic, Antun; Hsu, Chi-Ping; Jackson, M.A.B.

doi:10.1145/266021.266076

Cited by 3 publications

(1 citation statement)

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“…Without these advances, the semiconductor and electronics industries will suffer an economic death as they fall off the productivity curve [Be97].…”

Section: Introductionmentioning

confidence: 99%

An integrated flow for technology remapping and placement of sub-half-micron circuits

Lou

Salek²,

Pedram³

Proceedings of 1998 Asia and South Pacific Design Automation Conference

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-This paper presents a new design flow, FPDSiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic partitioning, floorplanning, global routing, and timing analysis/budgeting steps, followed by technology remapping and detailed placement of the selected logic clusters. The strength of the approach lies in the dynamic programming-based algorithm, SiMPA-D, used for performing simultaneous technology mapping and linear placement of logic clusters. This algorithm generates a set of solutions for each cluster, all of which are noninferior (in terms of gate area, cutwidth and delay), and hence permits trade-offs between total area (gate plus wiring) and total delay (gate plus wiring). Experimental results from a large number of MCNC benchmarks have proved the effectiveness of the proposed flow.

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“…Without these advances, the semiconductor and electronics industries will suffer an economic death as they fall off the productivity curve [Be97].…”

Section: Introductionmentioning

confidence: 99%

An integrated flow for technology remapping and placement of sub-half-micron circuits

Lou

Salek²,

Pedram³

Proceedings of 1998 Asia and South Pacific Design Automation Conference

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Logical-physical co-design for deep submicron circuits: challenges and solutions

Pedram

Proceedings of 1998 Asia and South Pacific Design Automation Conference

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{ As IC fabrication capabilities extend down to sub-half-micron, the signi cance of interconnect delay a n d p o wer dissipation can no longer be ignored. Existing enhancements to synthesis and physical design tools have n o t been able to solve the problem. The only remaining alternative is that tradeo s in logical and physical domains must be addressed in an integrated manner. Vast business opportunities will be lost unless more revolutionary changes to design ow are made. This paper discusses three technologies which a r e k ey to performing logic synthesis and physical layout optimization in tandem. They are early oorplanning, layout-driven logic synthesis, and post-layout resynthesis.

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