An integrated flow for technology remapping and placement of sub-half-micron circuits

Lou, Jinan; Salek, Amir; Pedram, Massoud

doi:10.1109/aspdac.1998.669472

Cited by 7 publications

(3 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In addition, placement is among the operations performed very early during physical design that can largely alter the physical implementation of the circuit. The algorithms provided in [LSP97] and [LSP98] (which are the earlier presentations of the algorithms proposed in this paper) for the first time merge the aforementioned design steps and provide a unified design step. The details of this approach and the proposed algorithms are given throughout this paper.…”

Section: Ii33 Unified Approachmentioning

confidence: 99%

An integrated logical and physical design flow for deep submicron circuits

Salek

Lou

Pedram

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

Section: Ii33 Unified Approachmentioning

confidence: 99%

An integrated logical and physical design flow for deep submicron circuits

Salek

Lou

Pedram

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…In these experiments, we have used an industrial standard cell library (0.35u CMOS process) that contains 34 buffers. Gate and wire delays are calculated using a 4-parameter delay equation [LSP98] and the Elmore delay [El48], respectively.…”

Section: Resultsmentioning

confidence: 99%

MERLIN: semi-order-independent hierarchical buffered routing tree generation using local neighborhood search

Salek¹,

Lou²,

Pedram³

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)

Self Cite

View full text Add to dashboard Cite

-This paper presents a solution to the problem of performance-driven buffered routing tree generation in electronic circuits. Using a novel bottom-up construction algorithm and a local neighborhood search strategy, this method finds the best solution of the problem in an exponential size solution subspace in polynomial time. The output is a hierarchical buffered rectilinear Steiner routing tree that connects the driver of a net to its sink nodes. The two variants of the problem, i.e. maximizing the driver required time subject to a total buffer area constraint and minimizing the total buffer area subject to a minimum driver required time constraint, are handled by propagating three-dimensional solution curves during the construction phase. Experimental results prove the effectiveness of this technique compared to the other solutions for this problem.

show abstract

“…SiMPA-D ('D' stands for disjoint combination based) combines LA and KA and optimizes total area and total delay by generating three dimensional trade-off curves for tree circuits [LSP98]. FPD-SiMPA (FPD stands for floorplan driven) is a design flow which incorporates SiMPA-D and SiMPA-E (SiMPA-D/E) for building two dimensional implementations for DAG-structure circuits [LSP98]. The outline of this design flow is as follows: 1.…”

Section: Introductionmentioning

confidence: 99%

A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together

Salek¹,

Lou²,

Pedram³

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)

Self Cite

View full text Add to dashboard Cite

INTRODUCTIONThe strong desire for ever-increasing levels of integration and higher performance often transcends the capabilities of traditional design tools and flows in the IC design arena. In particular, new deep-sub-micron (DSM) design considerations, such as the dominance of interconnect delays and signal integrity issues, have forced IC designers to reevaluate the existing design methodologies and techniques. To address the DSM design challenges, one can increase the lookahead capability of high-level tools or develop new algorithms for optimally solving larger portions of the overall design problem simultaneously. This latter unification-based approach is, in our view, more promising. Indeed, the current state of CAD tools and algorithms has evolved to a point where it is both possible and necessary to combine certain steps of the logic synthesis and physical design processes. This paper introduces an integrated approach for simultaneous floorplanning, technology-mapping, and detailed gate placement, of row-based standard-cell layout styles. The unique contributions of the paper are:•A new design flow, *SiMPA, which simultaneously performs floorplanning, technology mapping, and placement.•A new data structure, k-way levelized cluster tree, which represents the hierarchy of the circuit for *SiMPA.•A new global area optimizer, *SiMPA-E, which optimizes chip area via simultaneous floorplanning, technology mapping, and gate placement.•A new critical path optimizer, *SiMPA-R, which for a given number of critical paths effectively trades area for delay while simultaneously considering all floorplanning, technology mapping, and gate placement solutions.The rest of this paper is organized as follows. In section 2, background and motivation behind this work are given. Section 3 describes our methodology for unifying floorplanning, technology mapping, and gate placement. In sections 4 and 5, our experimental results and concluding remarks are presented. MINCUT is the LP problem where the cost function is the maximum cutwidth. It has been proven that this problem is NP-complete for general graphs [GJ79] but that it is polynomial in cases where the subject graph is a tree. Lengauer,in [Le82], developed an approximation algorithm (LA) for tree MINCUT problem whose cutwidth is within a factor of two of the optimal value. Later, Yannakakis introduced a polynomial optimal algorithm (YA) for tree MINCUT problem using the DP strategy [Ya85]. BackgroundSiMPA -To address the high performance requirements of DSM designs, SiMPA (Simultaneous Technology Mapping and Linear Placement Algorithm) integrates technology mapping and linear placement by combining DP-based YA/ LA with KA. This algorithm allows TM to access accurate physical information and LP to guide logic optimization. SiMPA-E ('E' stands for exact total area) is a combination

show abstract

An integrated flow for technology remapping and placement of sub-half-micron circuits

Cited by 7 publications

References 13 publications

An integrated logical and physical design flow for deep submicron circuits

An integrated logical and physical design flow for deep submicron circuits

MERLIN: semi-order-independent hierarchical buffered routing tree generation using local neighborhood search

A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together

Contact Info

Product

Resources

About