An integrated logical and physical design flow for deep submicron circuits

Salek, Amir; Lou, Jinan; Pedram, Massoud

doi:10.1109/43.784122

“…[5] and [11] describe approaches where floor planning information is used to support behavioral synthesis and can hence be seen as a form of prototyping. Beyond area and routability, performance and timing are an important concern [1][10] [13].The authors of [17] describe an algorithm which simultaneously addresses logic synthesis and placement. [16] describes a more comprehensive hierarchical floorplanning methodology addressing the performance and timing budgeting issues.…”

Section: Previous Workmentioning

confidence: 99%

Design flow and methodology for 50M gate ASIC

Mehrotra

¹

,

Ginneken

²

,

Trivedi

³

2003

Proceedings of the 2003 Conference on Asia South Pacific Design Automation - ASPDAC

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“…There have been many recent attempts to integrate logic synthesis and technology mapping with placement (that approximate global routes by bounding boxes or trees) (e.g., [10,11]). However, although this physical synthesis tries to comprehend the capacitive load of wires, the metrics that drive it are still the traditional literal or gate counts and fanout-based wire load metrics, sometimes augmented with estimated wirelengths.…”

Section: Logic Synthesis and Technology Mappingmentioning

confidence: 99%

“…Thus, without actually using any CbC structural fabric, this approach embodies the core principles of CbC design. There has been some early work in this direction (e.g., [10]), but it needs to be extended with a consideration of extensive unclocked and clocked repeaters.…”

Section: Block Constructionmentioning

confidence: 99%

The scaling challenge

Saxena

¹

,

Menezes

²

,

Cocchini

³

et al. 2003

Proceedings of the 2003 International Symposium on Physical Design

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We present the results of scaling studies in the context of typical block-level wiring distributions, and study the impact of the identified trends on the post-RTL design process. In particular, we look at the implications of exponentially increasing repeater and clocked repeater counts on the algorithms and methodologies used for logic synthesis, technology mapping, layout, and full-chip assembly, and identify several new research problems relevant to future designs. Next, we introduce the basic principles of correctby-construction (CbC) design. We look at some techniques for post-RTL design meeting CbC philosophy, and then construct a case for flexible, abstract fabrics. Finally, we suggest CbC approaches to tackle the new synthesis and layout challenges identified in this paper.

show abstract

“…[5] and [11] describe approaches where floor planning information is used to support behavioral synthesis and can hence be seen as a form of prototyping. Beyond area and routability, performance and timing are an important concern [1][10] [13].The authors of [17] describe an algorithm which simultaneously addresses logic synthesis and placement. [16] describes a more comprehensive hierarchical floorplanning methodology addressing the performance and timing budgeting issues.…”

Section: Previous Workmentioning

confidence: 99%