Design flow and methodology for 50M gate ASIC

Mehrotra, Alok; Ginneken, Lukas van; Trivedi, Yatin

doi:10.1145/1119772.1119917

Cited by 14 publications

(3 citation statements)

References 20 publications

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“…Particularly, note that many current designs are hierarchical and are designed top-down [14], [16], [8]. As pointed out in [8], floorplanning is becoming increasingly important for prototyping hierarchical designs.…”

Section: B Modern Fixed-outline Floorplanningmentioning

confidence: 99%

Fixed-outline floorplanning: enabling hierarchical design

Adya

Markov

2003

IEEE Trans. VLSI Syst.

329

221

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Abstract-Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show that instances of the fixed-outline floorplan problem are significantly harder than related instances of classical floorplan problems.

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Section: B Modern Fixed-outline Floorplanningmentioning

confidence: 99%

Fixed-outline floorplanning: enabling hierarchical design

Adya

Markov

2003

IEEE Trans. VLSI Syst.

329

221

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“…The hierarchical physical design method is very useful in designing large scale LSIs, but it is necessary to budget the delay between FFs in different hierarchical blocks [1]. The simplest method [2], based on the try-and-try-again strategy, repeats budgeting and block-level and LSI-level physical design many times.…”

Section: Conventional Approacesmentioning

confidence: 99%

“…Hierarchal design is very easy when the operating frequency of the LSI is relatively low but is very difficult for highfrequency LSIs because of the budgeting problem [1] [2]. In general, this is the problem of dividing one clock cycle among the different segments of the path from a flip-flop (FF) in one hierarchical block to a FF in another block.…”

Section: Introductionmentioning

confidence: 99%

Budgeting-free hierarchical design method for large scale and high-performance LSIs

Nakamura

Tagata

Okamoto

et al. 2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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This paper describes a new hierarchical design method for large scale and high-performance LSIs, which eliminates the need to perform budgeting. The budgeting step in hierarchical design partitions the total propagation time constraint for a path between any two flip-flops (FFs) in different hierarchical blocks into budgets for the different segments of the path that lie within different blocks. In practice, budgeting may result in the need for additional iterations of the synthesis and physical design flow, or may achieve suboptimal results in terms of area, power, or clock frequency. The proposed method makes the design process budgeting-free by moving the borders of the hierarchical blocks so that all borders of the hierarchical blocks are FFs. For a commercial 500MHz LSI with 141 million transistors, the design team required 2 months to archive the target frequency through try-and-try-again budgeting, while our budgeting-free method produced a design that meets the performance target within days.

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Introduction

2008

Wireless Transceiver Systems Design

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Design flow and methodology for 50M gate ASIC

Cited by 14 publications

References 20 publications

Fixed-outline floorplanning: enabling hierarchical design

Fixed-outline floorplanning: enabling hierarchical design

Budgeting-free hierarchical design method for large scale and high-performance LSIs

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