Improved delay prediction for on-chip buses

Pomerleau, R.; Frazon, Paul D.; Bilbro, Griff L.

doi:10.1145/309847.309986

Cited by 5 publications

(1 citation statement)

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“…Delay prediction is still an open research area across multi-time scale levels, ranging from nanosecond time scale [4], to larger time-scale within the range of few seconds when communicating through satellite link for example [5]. In this context, network delay forecast is of great interest in network-based applications, where the quality of information available in real-time is often a major constraint.…”

Section: Introductionmentioning

confidence: 99%

Modeling and Prediction of the Internet End-to-end Delay using Recurrent Neural Networks

Belhaj¹,

Tagina²

2009

JNW

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This paper focuses on modeling and predicting the Internet end-to-end (e2e) delay multi-step ahead using Recurrent Neural Networks (RNNs). In this work, Round- Trip Time (RTT) is used as the basic metric to forecast the Internet e2e delay. A method for delay prediction model is developed using RNNs, able to model nonlinear systems. By observing the delay between two Internet nodes, RTT data has been collected as a time series during several days. Then this discrete-time series data has been organized into two parts, the first one is used as a training/learning set of the RNN, whereas the rest of data is used for the testing/evaluation of the RNN performance. To achieve this purpose, a learning phase has been performed to provide a mathematical characterization of RTT during one or several reference days. The test phase consists of iteratively forecasting RTT acquired during the test day. Simulation results illustrate that the suggested model is adaptive and it tracks RTT dynamics rapidly and accurately, even for long time ahead prediction.

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Section: Introductionmentioning

confidence: 99%

Modeling and Prediction of the Internet End-to-end Delay using Recurrent Neural Networks

Belhaj¹,

Tagina²

2009

JNW

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Latency-guided on-chip bus network design

Drinic¹,

Kirovski²,

Meguerdichian³

et al.

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH3714

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Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in critical paths being dominated by global interconnect rather than gate delays. Second, ultra high level of integration mandates design of systems-on-chip that encompass nuinerous intra-synchronous blocks with decreased functional granularity and increased communication demands. To address these issues we have developed an on-chip bus network design methodology and corresponding set of tools which, for the first time, close the synthesis loop between system and physical design. The approach has three components: a communication profiler, a bus network designer, and a fast approximate floorplanner. The communication profiler collects run-time informat,ion about the traffic between system cores. The bus network dcsign componcxit optimixcs thc bus network structure by coordinating information from the other two components. The floorplanner aims at creating a feasible floorplan and to communicate information about the most constrained parts of the network. 1 lntrodiiction Due to design coniplcsit,y and tiine-to-mark(:t prcssurc, it is expected that futurc systems-on-chip arc dcsigned its networks of virtual components. Virtual componexit (VC) is a core wrapped with logic that enables it to 1 / 0 dat,iL to the attached bus with an nr1,itrary bus protocol 171. Bwause

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