Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance

Chowdhury, Masud H.; Ismail, Yehea; Kashyap, Chandramouli; Krauter, B.

doi:10.1109/iscas.2002.1010423

Cited by 33 publications

(20 citation statements)

References 17 publications

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“…Inductive coupling [11,12] takes worst form when both of the interconnect lines which are adjacent have same transition (i.e., either from 0 to 1 (↑↑) or from 1 to 0 (↓↓)). In this case leftmost aggressor line induces magnetic field on victim line which tends to flow a current which is in opposite direction with respect to the original current [5,11].…”

Section: Power and Crosstalk In Rlc Modeled Interconnectsmentioning

confidence: 99%

“…So crosstalk occurs between two interconnects which is presently the major problem in DSM technology. Therefore, in RLC model interconnects, when the lines are switching in same direction, then the worst case (↑↑↑ or ↓↓↓) [12] coupling occurs. Consequently, for RC modeled interconnects, worst case crosstalk delay occurs when adjacent lines are switched in opposite direction.…”

Section: Power and Crosstalk In Rlc Modeled Interconnectsmentioning

confidence: 99%

See 1 more Smart Citation

Crosstalk Reduction Using Novel Bus Encoders in Coupled RLC Modeled VLSI Interconnects

Babu

Kaushik

Bulusu

2012

Advances in Intelligent and Soft Computing

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Abstract. Most of the encoding methods proposed in recent years have dealt with only RC modeled VLSI interconnects. For deep submicron (DSM) technologies, on-chip inductive effects has rapidly increased due to increasing clock frequency, decreasing signal rise times and increasing length of on-chip interconnects. This issue is an important concern for signal integrity and overall chip performance. Therefore, this research paper proposes an efficient Bus Encoder using Bus Inverting (BI) method. This method dramatically reduces both crosstalk and power dissipation in RLC modeled interconnects. The proposed encoder consumes significantly lower power which makes it suitable for the current high-speed low power VLSI interconnects. The proposed design demonstrates an overall reduction in power dissipation and crosstalk delay by 59.43% and 72.87%, respectively.

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Section: Power and Crosstalk In Rlc Modeled Interconnectsmentioning

confidence: 99%

Section: Power and Crosstalk In Rlc Modeled Interconnectsmentioning

confidence: 99%

Crosstalk Reduction Using Novel Bus Encoders in Coupled RLC Modeled VLSI Interconnects

Babu

Kaushik

Bulusu

2012

Advances in Intelligent and Soft Computing

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“…It has been demonstrated that the signal behavior of coupled lines will be significantly different when inductances (self and mutual) are included (see Fig. 1 and [2,11]); and inductance can be exploited to improve some aspects of high speed integrated circuit performance. In [2] it is shown that depending on the circuit and signal condition the error due to neglecting inductances can be more than 100% for the delay calculation and 70% in the rise time calculation.…”

Section: Introductionmentioning

confidence: 99%

Behavior and Analysis of Deep Sub-micron Integrated Circuits Including Self and Mutual Inductances

Chowdhury

Ismail²

2008

Circuits Syst Signal Process

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Here a set of Elmore-like closed form solutions to analyze the behavior of integrated circuits in the presence of self and mutual inductances is presented. These expressions have linear complexity with the number of elements in the interconnect network, and Elmore delay accuracy characteristics. Besides the use of these expressions in evaluating signal characteristics, the simplicity of the solutions allows an intuitive understanding of the behavior of integrated circuits in the presence of self and mutual inductances together with capacitive coupling. Three problems are analyzed based on these solutions. First, a simple figure of merit to determine the importance of inductance in a bus is introduced. Second, the problem of shielding inductive coupling is investigated analytically. It is shown that inserting ground lines is not very effective in reducing inductive coupling compared to the differential signaling technique. Finally, the delay uncertainty due to different line-switching patterns is investigated. It is shown that inductive coupling reduces the delay variation (switching window width). With these applications of the delay model the opposite impacts of capacitive and inductive coupling in different signal switching patterns are illustrated with reference to the work of Kahng, Muddu, and Sarto.

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“…On-chip inductance effects in high-performance circuit designs might affect interconnect in many ways. The performance of a circuit will be reduced due to the increase of wire delay [5], [13]. The long-range inductive crosstalk can cause serious signal integrity related problems [9], [13].…”

Section: Introductionmentioning

confidence: 99%

RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction

Chang

Jou

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper shows that the worst case switching pattern that incurs the longest bus delay while considering the RLC effect is quite different from that while considering the RC effect alone. It implies that the existing encoding schemes based on the RC model may not improve or possibly worsen the delay when the inductance effects become dominant. A bus-invert method is also proposed to reduce the on-chip bus delay based on the RLC model. Simulation results show that the proposed encoding scheme significantly reduces the worst case coupling delay of the inductance-dominated buses.Index Terms-Bus-invert method, coupling, inductance, interconnect delay, worst case switching pattern.

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Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance

Cited by 33 publications

References 17 publications

Crosstalk Reduction Using Novel Bus Encoders in Coupled RLC Modeled VLSI Interconnects

Crosstalk Reduction Using Novel Bus Encoders in Coupled RLC Modeled VLSI Interconnects

Behavior and Analysis of Deep Sub-micron Integrated Circuits Including Self and Mutual Inductances

RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction

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