Latency-guided on-chip bus network design

Drinic, M.; Kirovski, D.; Meguerdichian, S.; Potkonjak, M.

doi:10.1109/iccad.2000.896508

Cited by 29 publications

(11 citation statements)

References 12 publications

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“…However, they assumed the bus topology to be given. Thepayasuwan et al [7] and Drinic et al [10] propose approaches which takes into consideration an estimate of the final layout of the design to generate a bus topology. However, neither of these approaches considers the effect of different communication parameters on system performance during synthesis.…”

Section: Related Workmentioning

confidence: 99%

Automated throughput-driven synthesis of bus-based communication architectures

Pasricha¹,

Dutt²,

Ben-Romdhane³

2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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As System-on-Chip (SoC) designs become more complex, it becomes increasingly harder to design communication architectures which satisfy design constraints. Manually traversing the vast communication design space for constraintdriven synthesis is not feasible anymore. In this paper we propose an approach that automates the synthesis of bus-based communication architectures for systems characterized by (possibly several) throughput constraints. Our approach accurately and effectively prunes the large communication design space to synthesize a feasible low-cost bus architecture which satisfies the constraints in a design.

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Section: Related Workmentioning

confidence: 99%

Automated throughput-driven synthesis of bus-based communication architectures

Pasricha¹,

Dutt²,

Ben-Romdhane³

2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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“…Nandi and Marculescu use continuous-time Markov process technique for performance measurement [13]. Drinic et al used the profiled statistics of inter-core traffic for core-to-bus assignment [14]. Thepayasuwan and Doboli propose a simulated annealing approach [15].…”

Section: Related Workmentioning

confidence: 99%

An Accurate and Fast Trace-aware Performance Estimation Model For Prioritized MPSoC Bus With Multiple Interfering Bus-Masters

Shafiq

Isshiki

2017

IPSJ Transactions on System LSI Design Methodology

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Accurate and fast performance estimation methods for modern and future multi-core systems are the focal point of much research due to the complexity associated with such architectures. The communication architecture of such systems has a huge impact on the performance and power of the whole system. Architects need to explore many design possibilities by using performance estimation techniques at early stages of design to make design decisions earlier in the design cycle. While software developers need to develop and test applications for the target architecture and gather performance measurements as early in the design cycle as possible. Full system simulation techniques provide accurate performance values but are extremely time consuming. Static analysis techniques are fast but cannot capture the dynamic behavior associated with shared resource contention and arbitration. Moreover, synthetic traffic patterns have been used to analyze the communication architecture however, such patterns are not realistic enough. We propose a statistical based model to predict the dynamic cost of bus arbitration on the performance of a bus architecture. The proposed model uses workload trace of the actual applications and benchmarks to capture the real application traffic behavior. Statistics on the traffic patterns are collected and input to the analytical model which calculates performance values for the communication architecture under consideration. By knowing the performance measures, designers can avoid over and under-design of the communication architecture. This paper builds up on a previously developed performance estimation model. The previous work modeled single and burst bus-transfers, however only one interfering bus master at a time for each blocked bus request was considered. The proposed, improved accuracy model considers multiple interfering masters for each blocked request hence improving the estimation accuracy especially for traffic intensive applications and many PE architectures. Experiments are performed for two different architectures i.e., 4 processing elements connected via a shared bus and 8 processing elements connected via a shared bus. Results show no significant difference in accuracy compared to previously developed model, for low traffic applications SPARSE and ROBOT however notable accuracy improvement for traffic intensive applications. Maximum estimation error is reduced from 1.75% to 0.6% for FPPPP and from maximum 13.91% to 8.8% for FFT on the 4PE architecture. On the 8PE architecture, maximum estimation error is reduced from 11.8% to 2.7% for the FPPP benchmark. Moreover simulation speed-up for the proposed technique over simulation method is reported.

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“…More precisely, the topology of a network (i.e how to shape a network) became a key parameter to determine the overall performance of a communication network. To deal with this problem, topology synthesis methods for the multi-layered bus architecture were introduced to determine a network topology in an automated fashion [4]. However, the multi-layered bus architecture inherently has a scalability issue which becomes worse as the number of components in a single chip increases.…”

Section: Introductionmentioning

confidence: 99%

InterSociety Conference on Thermal Phenomena in Electronic Systems. I-THERM II (Cat. No.90CH2798-7)

1990

InterSociety Conference on Thermal Phenomena in Electronic Systems

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The crossbar (also called bus matrix) solution is known as one of the most effective communication architectures for modern high-performance embedded systems. To make it even more effective, several topology synthesis methods have been proposed. They mostly generate a crossbar network in a cascaded fashion under the assumption that each crossbar switch is fully-connected (i.e. each input has a connection to every output). This assumption often limits optimizing the area efficiency and/or performance of the network, due to the unnecessary connections inside the crossbar switches. Some existing methods marginally improve their synthesis results by eliminating the unnecessary connections after the synthesis step. Such post-processing approaches make sense, since considering partially-connected crossbar switches earlier in the synthesis flow can greatly increase the optimal topology search space, thereby increasing the runtime. However, the result from these post-processing techniques is typically far inferior to that from the exhaustive search. In this work, we tackle such limitations of previous methods by introducing a heuristic method based on iterative switch merging. To the best of authors' knowledge, none of previous methods consider the partial connection of crossbar switches in the middle of the topology synthesis. Our experimental results prove the effectiveness of the proposed method by showing up to 30.35% of area saving against those methods that consider the partial connection only in a post-process. The results also show the superiority of the proposed method against the existing topology synthesis methods, showing up to 49.09% area saving and synthesis time reduction by several orders of magnitude.

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Latency-guided on-chip bus network design

Cited by 29 publications

References 12 publications

Automated throughput-driven synthesis of bus-based communication architectures

Automated throughput-driven synthesis of bus-based communication architectures

An Accurate and Fast Trace-aware Performance Estimation Model For Prioritized MPSoC Bus With Multiple Interfering Bus-Masters

InterSociety Conference on Thermal Phenomena in Electronic Systems. I-THERM II (Cat. No.90CH2798-7)

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