Physical and electrical design features of the IBM Enterprise System/9000 circuit module

Davidson, E.; Hardin, P.W.; Katopis, G.A.; Nealon, M.; Wu, L. L.

doi:10.1147/rd.365.0877

Cited by 22 publications

(10 citation statements)

References 9 publications

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“…The TFW described as Case 3 in Table I is known to be sufficiently dense to handle all of these requirements. For C4s, bump densities of 2000 per square centimeter are state-of-the-art [12]. With a signal to power ratio for high speed operation, 1000 signal I/O per square centimeter is a good rule of thumb for sizing purposes.…”

Section: The Diepack-a Packaging Solutionmentioning

confidence: 99%

Long lossy lines (L/sup 3/) and their impact upon large chip performance

Davidson

McCredie²,

Vilkelis

1997

IEEE Trans. Comp., Packag., Manufact. Technol. B

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The semiconductor industry expects the performance of microprocessors to continue at its current rate of improvement; i.e., clock rates should double every two to three years. This is a commendable goal but it is also fair to question whether this is an achievable goal. The fundamental problem is that as groundrules are reduced, the natural tendency is to make smaller conductor cross-sectional areas. The result is a high resistance line that exhibits slow wave propagation effects [1]. This reduces the general performance expectations. As circuits become faster and denser on the chip, line delays become greater than expected. This problem will be analyzed and potential chip and packaging solutions will be offered. Clock rate predictions for various design and process options will be made. A tactical recommendation to consider a total packaged electronics solution is presented.Index Terms-High clock rate, high performance, large chip, large die, long line, lossy line, MCM, microprocessor, multichip module, submicron design.

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Section: The Diepack-a Packaging Solutionmentioning

confidence: 99%

Long lossy lines (L/sup 3/) and their impact upon large chip performance

Davidson

McCredie²,

Vilkelis

1997

IEEE Trans. Comp., Packag., Manufact. Technol. B

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“…of only a few millimeters as, for example, was done for the IBM ESI 9000 mainframe MCM packaging [11,13].…”

Section: Very Rough Estimate Of Acceptable Lead Inductance L = Lmaxmentioning

confidence: 99%

“…UBReB / Logical function [1][2][3][4][5][6][7][8][9][10][11][12][13][14] In the case of digital processors, the logical function of generalized blocks correspond to instructions of a processor and TB corresponds to instruction execution time: The progress in LSI technology has had a major effect on increasing the performance and reducing the cost of digital systems. The design concept of digital processors represented by Equation 1-15 and items 1-3 enables us to comprehend this effect.…”

Section: Power-time Product Theorymentioning

confidence: 99%

Microelectronics Packaging—An Overview

Rymaszewski

Tummala

Watari

1997

Microelectronics Packaging Handbook

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“…With the increase in active surface area of the substrate and the increase in electrical performance requirements, relatively long EC wires can no longer satisfy current requirements regarding impedance EC wiring and near-end coupled noise [32]. Although the use of coaxial wires and twistedpair wires can satisfy these requirements, their use is impractical because of the small physical dimensions available.…”

Section: Engineering Changesmentioning

confidence: 99%

Electrical connections to the thermal conduction modules of the IBM Enterprise System/9000 water-cooled processors

1992

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In a complex multichip carrier such as the thermal conduction module (TCM) of IBM high-performance mainframe processors, the interfaces between chips and their substrate as well as between the substrate and its printed circuit board must support a large number of electrical connections. Since chip, substrate, and board typically comprise very different materials, the electrical connections between them must be able to accommodate considerable thermally induced mechanical stress during assembly and use. This paper describes the pin attachment, chip attachment. wire bonding, and laser deletion processes used for forming the electrical connections to theglass-ceramic/copper/polyimide/copper substrate of the thermal conduction modules of the IBM Enterprise System/9000™ watercooled processors.

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Physical and electrical design features of the IBM Enterprise System/9000 circuit module

Cited by 22 publications

References 9 publications

Long lossy lines (L/sup 3/) and their impact upon large chip performance

Long lossy lines (L/sup 3/) and their impact upon large chip performance

Microelectronics Packaging—An Overview

Electrical connections to the thermal conduction modules of the IBM Enterprise System/9000 water-cooled processors

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