Long lossy lines (L/sup 3/) and their impact upon large chip performance

Davidson, E.; McCredie, B.D.; Vilkelis, W. V.

doi:10.1109/96.641504

Cited by 35 publications

(14 citation statements)

References 9 publications

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“…If there are k repeaters the rcl 2 delay is replaced by k(rc(l/k) 2 ) (Davidson et al 1997). Ten repeaters could reduce wire delays by a factor of 10, although some time would be added by delays in the repeater circuits.…”

Section: Long Wire Delaysmentioning

confidence: 99%

Physical limits of silicon transistors and circuits

2005

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A discussion on transistors and electronic computing including some history introduces semiconductor devices and the motivation for miniaturization of transistors. The changing physics of field-effect transistors and ways to mitigate the deterioration in performance caused by the changes follows. The limits of transistors are tied to the requirements of the chips that carry them and the difficulties of fabricating very small structures. Some concluding remarks about transistors and limits are presented.

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Section: Long Wire Delaysmentioning

confidence: 99%

Physical limits of silicon transistors and circuits

2005

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“…Moreover, because of the higher operational frequencies and lower resistivity copper interconnects, inductive impedance of the on-chip wires become comparable to or larger than the resistive impedance. Due to these reasons, on chip capacitive and inductive effects have enormous effects on the signal integrity and performance of today's copper (Cu) based nano-interconnects [1], [2]. Again, the resistivity of copper increases in the nanometric regime due to surface and grain boundary scattering [3], which deteriorates the performance of especially long intermediate and global interconnects.…”

Section: Introductionmentioning

confidence: 99%

Impact of Inductance on the Performance of Single Walled Carbon Nanotube Bundle Interconnects

Sahoo

Rahaman

Bhattacharya

2013

2013 International Symposium on Electronic System Design

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In this work, we have studied the inductive properties of interconnects built with Single Walled Carbon Nanotube (SWCNT) bundle. We have used the most recent ITRS-2011 data while estimating the RLC parameters of SWCNT bundle interconnects. In our analysis, we have used the classical ABCD-parameter-matrix based method and a delay allowance of 50%. Simulations are performed for both sparse and dense SWCNT bundle interconnects at 21 nm and 15 nm technology nodes, considering three levels of their application: local, intermediate, and global. It is observed that for a 100 MHz periodic square wave input with a rise time of 10 ps, SWCNT bundle interconnects are not impacted by inductance. It is shown that for the given input signal and SWCNT bundle parameters, the length over which the inductive effects will be more prominent, has little practical significance. It is quantitatively shown that the inductive effects will mostly impact the long-intermediate and global interconnects. With technology scaling, such effects may worsen the performance. It is also observed that the Elmore-based methodology for delay estimation of SWCNT bundle interconnects predicts the actual delay very accurately with a maximum error of only 5.46%.

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“…As a result, interconnect delay in long global wires is an increasing problem in integrated circuits (IC) relative to delays in transistor switching [1], [2]. In the latest microelectronics technology nodes, interconnect delay has become the limiting factor in determining the speed of digital systems [3].…”

Section: Introductionmentioning

confidence: 99%