Ph.D. Forum Abstract: Back to the Future - Sustainable Transiently Powered Embedded Systems

Bhatti, Naveed Anwar

doi:10.1109/ipsn.2016.7460686

Cited by 7 publications

(19 citation statements)

References 3 publications

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“…Compile time checkpoint triggering implementations, e.g. [27], [28], [29], [30], [31], [32] introduce minimum overhead for the programmer. For example, in [28], the triggering points are placed after each loop unroll and each function return compares the input voltage (V in ) against a threshold and performs a checkpoint if V in is below the threshold.…”

Section: Related Workmentioning

confidence: 99%

Intermittent Computing Emulation of Ultralow-Power Processors: Evaluation of Backup Strategies for RISC-V

Philip

Yıldırım

Brunelli

2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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With the progress in energy harvesting circuits and the decrease in power requirements of processing, sensing, and communication hardware, we have the potential of freeing the Internet of Things devices from their batteries. However, removing batteries introduces frequent power failures due to the irregular power availability from the environment. This situation leads devices to compute intermittently under transient environmental power. Intermittent computing requires significant microarchitectural modifications on existing processor designs to ensure automatic computation progress despite the power failures. For example, built-in nonvolatile memory components should be integrated in processor architectures. Consequently, different microarchitectural automatic backup strategies need to be implemented. In this work, we introduce different processor state backup strategies based on an interrupt-based software approach, which do not need modifications to the microarchitecture of existing processors. Therefore, we present a systematic approach to emulate different processor architectures with varying backup strategies under transient power. To justify our claims, we make Ibex RISC-V core, a popular ultra-low-power processor architecture, suitable for intermittent computing. This is the first attempt to make a variety of existing and future ultra-low-power processor architectures easily exploitable for transiently-powered computing systems.

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Section: Related Workmentioning

confidence: 99%

Intermittent Computing Emulation of Ultralow-Power Processors: Evaluation of Backup Strategies for RISC-V

Philip

Yıldırım

Brunelli

2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…A significant fraction of existing solutions employ a form checkpointing to cross power failures [3,7,11,36,46]. This consists in replicating the content of main memory, special registers, and program counter onto non-volatile memory at specific points in the code.…”

Section: Related Workmentioning

confidence: 99%

“…Systems such as Hibernus [7,8] operate in a reactive manner: an interrupt is fired from a hardware device that prompts the application to take a checkpoint, for example, whenever the energy buffer falls below a threshold. Differently, systems exist that place explicit function calls to perform checkpoints [11,36,46,49]. The specific placement is a function of program structure and energy patterns.…”

Section: Related Workmentioning

confidence: 99%

“…The program is first processed through the compile-time support an existing checkpoint system [7,8,11,29,36,46,49] or task-based programming abstraction [16,34,35,44,47,52]. Either way, at stage ⟨2⟩ the program includes state-save operations inlined in the execution flow as calls to a checkpointing subsystem or placed at task boundaries.…”

Section: Overviewmentioning

confidence: 99%

“…A computation interval consists in a sequence of machine-code instructions executed between two statesave operations. For programs using checkpoint mechanisms [7,8,11,29,36,46,49], computation intervals correspond to sequences of instructions between two checkpoint calls. For programs using taskbased programming abstractions [16,34,35,44,47,52], computation intervals essentially correspond to tasks.…”

Section: Overviewmentioning

confidence: 99%

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Alfred

Maioli

Mottola

2021

Proceedings of the 19th ACM Conference on Embedded Networked Sensor Systems

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We present ALFRED: a virtual memory abstraction that resolves the dichotomy between volatile and non-volatile memory in intermittent computing. Mixed-volatile microcontrollers allow programmers to allocate part of the application state onto non-volatile memory. Programmers are therefore to manually explore the tradeoff between simpler management of persistent state against energy overhead and possibility of intermittence anomalies due to nonvolatile memory operations. This approach is laborious and yields sub-optimal performance. We take a different stand with ALFRED: we provide programmers with a virtual memory abstraction detached from the specific volatile nature of memory and automatically determine an efficient mapping from virtual to volatile or non-volatile memory. Unlike existing works, ALFRED does not require programmers to learn a new language syntax and the mapping is entirely resolved at compile-time, reducing the run-time energy overhead. We implement ALFRED through a series of machine-level code transformations. Compared to existing systems, we demonstrate that ALFRED reduces energy consumption by up to two orders of magnitude given a fixed workload. This enables workloads to finish sooner, as the use of available energy shifts from ensuring forward progress to useful application processing. CCS CONCEPTS• Computer systems organization → Embedded software.

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Energy-Efficient Memory Tracing for State Retention in Transient Computing Systems

Verykios

Balsamo

Merrett

2023

2023 9th International Workshop on Advances in Sensors and Interfaces (IWASI)

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Transient computing systems, also known as intermittent computing systems, are batteryless systems powered by energy harvesting (EH) sources that do not require large energy storage for system operations. Instead, they rely on retaining their state, i.e. a snapshot, in non-volatile memory (NVM) in the event of a power outage and restoring it when the power recovers. In this paper, we first discuss the limitations of stateof-the-art techniques that attempt to minimize the amount of system state saved to NVM. Therefore, we propose a novel energy-efficient system-level approach for state retention through memory tracing based on a custom hardware module named MeTra that traces changes in the main (volatile) memory between power outages. MeTra allows the voltage threshold that activates the state retention process to be dynamically adjusted according to the energy requirement of each snapshot. Thus, a great proportion of the energy harvested can be spent on useful operations. Experimental results show that the system's active time can be extended up to 17x for Flash-based systems and 92.2% for FRAM-based systems, compared to saving the entire system state, with an area overhead of as little as 2.48%.

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Ph.D. Forum Abstract: Back to the Future - Sustainable Transiently Powered Embedded Systems

Cited by 7 publications

References 3 publications

Intermittent Computing Emulation of Ultralow-Power Processors: Evaluation of Backup Strategies for RISC-V

Intermittent Computing Emulation of Ultralow-Power Processors: Evaluation of Backup Strategies for RISC-V

Alfred

Energy-Efficient Memory Tracing for State Retention in Transient Computing Systems

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