Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

Abstract

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate-source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-κ gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on-off current ratio (I on /I off ).Based on the investigation of on-current (I on ), off-current (I off ), I on /I off , intrinsic delay (τ ), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/σ ) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I on , I off and τ is also investigated for optimized underlap devices.

Silicon-on-insulator (SOI) junctionless transistors

“…This is at the root of the short-channel effect reduction in junctionless transistors. This effect is somewhat similar to the reduction of DIBL in IM devices with gate underlap (Kranti et al , 2008). The variation of effective gate length, L eff , in a junctionless transistor is illustrated in Fig.…”

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

“…1b) was modeled using the expression N SD (x) = (N SD ) peak exp(-x 2 /r 2 ), where (N SD ) peak is the peak S/D doping, r (lateral straggle) defines the roll-off [13][14][15][16][17][18] of the Gaussian S/D profile as ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2sd=lnð10Þ p , s is the spacer width. The S/D doping gradient (d) which provides a measure of lateral doping abruptness was evaluated as (d = 1/|dN SD (x)/dx|) [13][14][15][16][17][18][19] at the front gate edge and was varied from 3 to 5 nm/decade. Lower d values represent a steeper doping gradient, whereas higher values signify a gradual S/D junction.…”

“…In this work, we propose a design methodology to alleviate the above two critical issues for ultra-low-voltage (ULV) analog/rf devices operating in the subthreshold and low moderate inversion regions. We use the concept of gate-underlap design which has been studied extensively for digital [12][13][14][15][16][17][18] and analog/rf [19][20][21][22][23] applications. In high-volume manufacturing, gate-source/drain underlap devices were 'accidentally' fabricated in 0.35 micron CMOS technology [24].…”

Optimization of parameters of double-gate sub-20 nanometers SOI CMOS transistors with architecture “without overlapping”

“…Summarizing the obtained results and data from works [4][5][6]8], we define the range of the change of the thickness of the working area from 6 nm to 10 nm and of the thickness of the gate dielectric of the frontal gate from 1.05 nm up to 3 nm. Then, for parameters t Si = 6 nm and t f = 1.05 nm, the value of characteristic length l is equal 10.97 nm, which is the minimal value in the considered case.…”

“…For simulation of nanodimensional devices, the approved model formulated within the limits of the drift diffusion approach [9] was used, after taking into consideration the modified expression for the speed of saturation and the model of mobility, which was mod ified to account for high field degradation [8]. The used modification of the expression of the speed of sat uration of the carriers provides a comprehensible esti mate of level I on in comparison with simulation by the Monte Carlo method for double gate transistors on a wide range of lengths of gates (10-100 nm).…”