Silicon-on-insulator (SOI) junctionless transistors

Colinge, J.P.

doi:10.1533/9780857099259.1.167

Cited by 5 publications

(5 citation statements)

References 76 publications

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“…The junctionless transistor is a very promising Metal-Oxide-semiconductor field effect transistor architecture based on a single type (N+N+N+ or P+P+P+) doping of source, drain and channel [13][14][15]. Junctionless FET represents an innovative class of field effects devices having no abrupt doping junctions.…”

Section: Introductionmentioning

confidence: 99%

“…This no-junction device is basically a resistor in which the mobile carrier density can be modulated by the device gate. Unlike its conventional MOSFET counterpart, the JLT offers diverses advantages such as : a simpler manufacturing process, a reduced propagation delay, a low electric field at ON state [16], volume conduction (in bulk), improved mobility and insensitive to gate / channel interface effects [15], dynamic power dissipation, and faster switching. It has been shown that the ideal MOSFETs threshold slope obtained is equal to 60 mV / decade actually; manufactured devices can not achieve this value due for exempleto the influence of interface traps.…”

Section: Introductionmentioning

confidence: 99%

“…Different works have been presented studying JLT devices such as bulk planar JLTFET [16], single gate silicon-on-insulator (SOI) JLFET [15], multi-gate nanowire junctionless transistors [17], gate-all-around nanowire junctionless transistors [18], as well as junctionless tunnel FET [19]. Our study allows us to design a 3D GAA junctionless transistor with rectangular cross section using ATLAS SILVACO software.…”

Section: Introductionmentioning

confidence: 99%

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DC performance analysis of a 20nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor

Merad

Guen-Bouazza

2020

IJECE

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With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport model .This new generation device is conceived with the same doping concentration level in its channel source/drain allowing to reduce fabrication complexity . The performance of our 3D JL-GAA structure with a 20nm gate length and a rectangular cross section have been obtained using SILVACO TCAD tools allowing also to study short channel effects. Our device reveals a favorable on/off current ratio and better SCE characteristics compared to an inversion-mode GAA transistor. Our device reveals a threshold voltage of 0.55 V, a sub-threshold slope of 63mV / decade which approaches the ideal value, an Ion / Ioff ratio of 10e + 10 value and a drain induced barrier lowring (DIBL) value of 98mV / V.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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DC performance analysis of a 20nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor

Merad

Guen-Bouazza

2020

IJECE

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“…Thirdly, the mobility in JLFET is improved and insensitive to the interface of gate oxide to channel due to its bulk conduction, unlike surface conduction in the inversion mode device, e.g. MOSFET [4]. It also offers more robust design as it is simple to produce in thin silicon layer.…”

Section: Introductionmentioning

confidence: 99%

“…A number of JLFET structures have been proposed with variations in topologies, such as single gate bulk planar JLFET [3], single gate silicon-on-insulator (SOI) JLFET [4], multi-gate nanowire junctionless transistors [5], gate-all-around nanowire junctionless transistors [6], as well as junctionless tunnel FET [7]. However, little attention is given on the gate materials in JLFET as well as the processing sequence on the gate.…”

Section: Introductionmentioning

confidence: 99%

Influence of Gate Material and Process on Junctionless FET Subthreshold Performance

Riyadi¹,

Sukawati²,

Prakoso³

et al. 2016

IJECE

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The recent progress of dimension scaling of electronic device into nano scale has motivated the invention of alternative materials and structures. One new device that shows great potential to prolong the scaling is junctionless FET (JLFET). In contrast to conventional MOSFETs, JLFET does not require steep junction for source and drain. The device processing directly influence the performance, therefore it is crucial to understand the role of gate processing in JLFET. This paper investigates the influence of gate material and process on subthreshold performance of junctionless FET, by comparing four sets of gate properties and process techniques. The result shows that in terms of subthreshold slope, JLFET approaches near ideal value of 60 mV/decade, which is superior than the SOI FET for similar doping rate. On the other hand, the threshold value shows different tendencies between those types of device.

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Investigation of Hot Carrier–induced Degradation in Nanoscale JunctionlessMOSFETs: A Reliability‐based Analysis

Abdelmalek¹,

Djeffal²,

Bentrcia³

2022

Nanotechnology in Electronics

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Silicon-on-insulator (SOI) junctionless transistors

Cited by 5 publications

References 76 publications

DC performance analysis of a 20nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor

DC performance analysis of a 20nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor

Influence of Gate Material and Process on Junctionless FET Subthreshold Performance

Investigation of Hot Carrier–induced Degradation in Nanoscale JunctionlessMOSFETs: A Reliability‐based Analysis

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