Performance of SiC cascode JFETs under single and repetitive avalanche pulses

Agbo, S.N.; Gonzalez, Jose Ortiz; Alatise, Olayiwola

doi:10.1016/j.microrel.2020.113644

Cited by 5 publications

(3 citation statements)

References 28 publications

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“…1.2 Drift layer thickness (µm) 6.0 Drift layer doping (cm -3 ) 2.33x10 16 Drain doping (cm -3 ) 1x10 19 Channel doping (cm -3 ) 2.33x10 16 JFET gate doping (cm -3 ) 1x10 19 Cell pitch (µm) 3.2 Area factor (µm) 6x10 5 Breakdown (V) 800…”

Section: Parametermentioning

confidence: 99%

“…In SiC Cascode JFETs, since a LV silicon MOSFET is used, the failure mode is different. For example, considering unclamped inductive switching (UIS), previous studies indicated the key role of the gate leakage current of the JFET during UIS conditions [18][19][20]. This paper aims to investigate the failure modes of SiC Cascode JFETs during SC conditions.…”

Section: Introductionmentioning

confidence: 99%

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Simulations and Measurements of Failure Modes in SiC Cascode JFETs under Short Circuit Conditions

Agbo

Bashar

et al. 2021

2021 IEEE 22nd Workshop on Control and Modelling of Power Electronics (COMPEL)

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Section: Parametermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Simulations and Measurements of Failure Modes in SiC Cascode JFETs under Short Circuit Conditions

Agbo

Bashar

et al. 2021

2021 IEEE 22nd Workshop on Control and Modelling of Power Electronics (COMPEL)

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“…These negative values indicate that the rated voltage of the SiC JFET is exceeded, which must be avoided. Even modest violations of the semiconductor voltage rating can compromise device lifetime if repetitive switching occurs under these conditions [34], [35].…”

Section: B Normalized Voltage Marginmentioning

confidence: 99%

Novel Figures of Merit for Evaluating the Performance of the Super-Cascode Switch

Jimenez,

Lemmon,

Boutry

2024

IEEE Open J. Power Electron.

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The super-cascode switch (SCS) has gained significant attention in the last decade due to its ability to achieve medium-voltage ratings using low-voltage semiconductors. However, there exists a notable absence of quantitative metrics to effectively evaluate the performance of the SCS. This gap exists because the behavior of the SCS is different from that of a traditional semiconductor switch, and traditional semiconductor performance metrics are not adequate for its evaluation. The present manuscript addresses this gap by introducing new figures of merit that are designed to evaluate the unique characteristics of the SCS. The practical value of these metrics is also demonstrated through a set of experimental studies. By applying these new figures of merit to one of the best-performing SCS configurations described previously in the literature, several opportunities for improvement are revealed. The SCS prototype described in this paper is evaluated experimentally at bus voltage levels up to 3.5 kV and current levels up to 200 A, demonstrating substantial performance improvements relative to the baseline configuration from the literature. These improvements are the result of iterative refinements to the balancing network, which are selected through a process that is informed by the application of the proposed figures of merit.

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Avalanche capability degradation of the parallel-connected SiC MOSFETs

Mao

Ran

Chen

et al. 2023

Microelectronics Reliability

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Performance of SiC cascode JFETs under single and repetitive avalanche pulses

Abstract: Please refer to published version for the most recent bibliographic citation information. If a published version is known of, the repository item page linked to above, will contain details on accessing it.

Cited by 5 publications

References 28 publications

Simulations and Measurements of Failure Modes in SiC Cascode JFETs under Short Circuit Conditions

Simulations and Measurements of Failure Modes in SiC Cascode JFETs under Short Circuit Conditions

Novel Figures of Merit for Evaluating the Performance of the Super-Cascode Switch

Avalanche capability degradation of the parallel-connected SiC MOSFETs

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