Novel Figures of Merit for Evaluating the Performance of the Super-Cascode Switch

Abstract

The super-cascode switch (SCS) has gained significant attention in the last decade due to its ability to achieve medium-voltage ratings using low-voltage semiconductors. However, there exists a notable absence of quantitative metrics to effectively evaluate the performance of the SCS. This gap exists because the behavior of the SCS is different from that of a traditional semiconductor switch, and traditional semiconductor performance metrics are not adequate for its evaluation. The present manuscript addresses this gap by introducing new figures of merit that are designed to evaluate the unique characteristics of the SCS. The practical value of these metrics is also demonstrated through a set of experimental studies. By applying these new figures of merit to one of the best-performing SCS configurations described previously in the literature, several opportunities for improvement are revealed. The SCS prototype described in this paper is evaluated experimentally at bus voltage levels up to 3.5 kV and current levels up to 200 A, demonstrating substantial performance improvements relative to the baseline configuration from the literature. These improvements are the result of iterative refinements to the balancing network, which are selected through a process that is informed by the application of the proposed figures of merit.

Design and Evaluation of a 6.5 kV, 400 A Super-Cascode Power Module

“…Therefore, the voltage distribution within the different stages of the SCS is inherently unbalanced. This imbalance results in an unequal static and dynamic performance of the switch [11], which will be empirically demonstrated in subsequent sections.…”

“…The second modification involves the addition of balancing resistors RD1-RD5 [6]. For the studied SCS topology, the introduction of these resistors helps minimize the voltage overshoot of each semiconductor at turn-off [11]. The third modification is the addition of the kelvin terminal as the return path for the gate loop.…”

“…This lack of gate control is well-known for the cascode topology [10]. However, as has been recently shown in [11], the gate resistor of the first stage, 𝑅 𝑆1 , can be harnessed to control the dynamic performance of the SCS. This time interval ends once all the transistors have finished their respective voltage transitions.…”

“…Consequently, an improved static voltage distribution among the transistors can be achieved, particularly in high-current operating conditions. In [11], a further enhancement of this calculation was proposed. This enhancement addressed the inclusion of the balancing capacitor in the upper stage of the SCS.…”

“…where 𝐶 𝐷𝑛 is the balancing capacitor under analysis counted from the LV Si MOSFET; 𝑝 is the number of paralleled die per stage; 𝑠 is the total number of stages in the SCS; 𝑛 is the stage number of the capacitor evaluated; 𝑄 𝐺 is the JFET gate charge; 𝑄 𝐷 is the balancing diode charge; and 𝑉 𝐷 𝐴𝑉 is the avalanche voltage of the balancing diodes. Equations for the gate JFET gate charge and the balancing diode charge are provided in [11], [22] and remain valid for this treatment.…”