Performance Evaluation of Matrix-Matrix Multiplications Using Intel's Advanced Vector Extensions (AVX)

In order to facilitate flexible network service virtualization and migration, network functions (NFs) are increasingly executed by software modules as so-called "softwarized NFs" on General-Purpose Computing (GPC) platforms and infrastructures. GPC platforms are not specifically designed to efficiently execute NFs with their typically intense Input/Output (I/O) demands. Recently, numerous hardwarebased accelerations have been developed to augment GPC platforms and infrastructures, e.g., the central processing unit (CPU) and memory, to efficiently execute NFs. This article comprehensively surveys hardware-accelerated platforms and infrastructures for executing softwarized NFs. This survey covers both commercial products, which we consider to be enabling technologies, as well as relevant research studies. We have organized the survey into the main categories of enabling technologies and research studies on hardware accelerations for the CPU, the memory, and the interconnects (e.g., between CPU and memory), as well as custom and dedicated hardware accelerators (that are embedded on the platforms); furthermore, we survey hardware-accelerated infrastructures that connect GPC platforms to networks (e.g., smart network interface cards). We find that the CPU hardware accelerations have mainly focused on extended instruction sets and CPU clock adjustments, as well as cache coherency. Hardware accelerated interconnects have been developed for on-chip and chip-to-chip connections. Our comprehensive up-to-date survey identifies the main trade-offs and limitations of the existing hardware-accelerated platforms and infrastructures for NFs and outlines directions for future research.

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“…Content may change prior to final publication. [116] AES-NI [117], [118] DRNG [119] AVX [120]- [123] SSE [124], [125] CPU Identi. [126] VM Ext.…”

Section: ) Instruction Set Acceleration (Isacc)mentioning

confidence: 99%

“…The Advanced Vector Extensions (AVX) [120], [121] implement an advanced data processing IS for machine learning, encryption, and signal processing [122]. The vectorization of the CPU processing significantly improves the data computations for large vector data sets [123].…”

Section: C: the Advanced Vector Extensions (Avx)mentioning

confidence: 99%

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

2020

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“…They can operate with single or double‐precision floating‐point variables and data types. The AVX supports fused multiply‐add (FMA) operations on vector registers as well . This SIMD approach can improve the performance of arbitrary applications through their data‐parallel execution, but the selection of suitable algorithm, programming model, and compiler is crucial for the success of AVX‐based vectorization.…”

Section: Avx Instructions and The Acceleration Of Jpeg Steganographymentioning

confidence: 99%

“…The use of AVX has a positive impact on the performance of implemented algorithms. Suitable data parallel operations such as vector and matrix operations can be accelerated by the factor of two and more . It can be also used to speed up stochastic methods such as Monte Carlo simulations, image processing tasks, etc.…”

Section: Introductionmentioning

confidence: 99%

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JPEG steganography with particle swarm optimization accelerated by AVX

Snášel

Krömer

Šafařík

et al. 2019

Concurrency and Computation

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Summary Digital steganography aims at hiding secret messages in digital data transmitted over insecure channels. The JPEG format is prevalent in digital communication, and images are often used as cover objects in digital steganography. Optimization methods can improve the properties of images with embedded secret but introduce additional computational complexity to their processing. AVX instructions available in modern CPUs are, in this work, used to accelerate data parallel operations that are part of image steganography with advanced optimizations.

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Fast matrix multiplication via compiler‐only layered data reorganization and intrinsic lowering

et al. 2023

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The resurgence of machine learning has increased the demand for high-performance basic linear algebra subroutines (BLAS), which have long depended on libraries to achieve peak performance on commodity hardware. High-performance BLAS implementations rely on a layered approach that consists of tiling and packing layers -for data (re)organization -and micro kernels that perform the actual computations. The algorithm for the tiling and packing layers is target independent but is parameterized to the memory hierarchy and register-file size. The creation of high-performance micro kernels requires significant development effort to write tailored assembly code for each architecture. This hand optimization task is complicated by the recent introduction of matrix engines by IBM ® 's POWER10 ™ (Matrix Multiply Assist -MMA), Intel ® (Advanced Matrix eXtensions -AMX), and Arm ® (Matrix Extensions -ME) to deliver high-performance matrix operations. This paper presents a compiler-only alternative to the use of high-performance libraries by incorporating, to the best of our knowledge and for the first time, the automatic generation of the layered approach into LLVM, a production compiler. Modular design of the algorithm, such as the use of LLVM's matrix-multiply intrinsic for a clear interface between the tiling and packing layers and the micro kernel, makes it easy to retarget the code generation to multiple accelerators. The parameterization of the tiling and packing layers is demonstrated in the generation of code for the MMA unit on IBM's POWER10. This paper also describes an algorithm that lowers the matrix-multiply intrinsic to the MMA unit. The use of intrinsics enables a comprehensive performance study. In processors without hardware matrix engines, the tiling and packing delivers performance up to 22× (Intel) -for small matrices -and more than 6× (POWER9) -for large matrices -faster than PLuTo, a widely used polyhedral optimizer. The performance also approaches high-performance libraries and is only 34% slower than OpenBLAS and on-par with Eigen for large matrices. With MMA in POWER10 this solution is, for large matrices, over 2.6× faster the vector-extension solution, matches Eigen performance, and achieves up to 96% of BLAS peak performance.

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Performance Evaluation of Matrix-Matrix Multiplications Using Intel's Advanced Vector Extensions (AVX)

Cited by 19 publications

References 11 publications

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

JPEG steganography with particle swarm optimization accelerated by AVX

Fast matrix multiplication via compiler‐only layered data reorganization and intrinsic lowering

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