Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Shantharama, Prateek; Thyagaturu, Akhilesh S.; Reisslein, Martin

doi:10.1109/access.2020.3008250

Cited by 62 publications

(43 citation statements)

References 266 publications

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“…Another work by Shantharama et al [19] surveyed the hardware-accelerated platforms and infrastructure for virtualization comprehensively. This survey categorized them into enabling technologies and research studies on hardware accelerations for CPU, memory, interconnects (between CPU and memory), and the custom & dedicated embedded accelerators.…”

Section: Introductionmentioning

confidence: 99%

Optimum Functional Splits for Optimizing Energy Consumption in V-RAN

Ismail

Mahmoud

2020

IEEE Access

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A virtualized radio access network (V-RAN) is considered one of the key research points in the development of 5G and the interception of machine learning algorithms in the Telecom industry. Recent technological advancements in Network Function Virtualization (NFV) and Software Defined Radio (SDR) are the main blocks towards V-RAN that have enabled the virtualization of dual-site processing instead of all BBU processing as in the traditional RAN. As a result, several types of research discussed the trade-off between power and bandwidth consumption in V-RAN. Processing at remote locations instead of BBU reduces mid-haul bandwidth at the expense of power consumption and vice versa. As a result, the integration of NFV and SDR in V-RAN facilitates dynamic power consumption and processing whenever relaxation is needed. This paper studies several functional splits proposed by ETSI in the NFV of the dualsite network. In addition, network performance is analyzed in terms of data rate, power consumption, and energy efficiency (EE) optimization. Furthermore, the combined optimization of power consumption and mid-haul bandwidth are investigated, and optimal operating parameters are recommended for similar network operators. Thus, regulators/operators can adjust their networks with these parameters to achieve the best performance. Additionally, the UEs switching scheme is introduced to sleep some RRHs in low-density traffic to lessen power consumption.

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Section: Introductionmentioning

confidence: 99%

Optimum Functional Splits for Optimizing Energy Consumption in V-RAN

Ismail

Mahmoud

2020

IEEE Access

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“…NFV introduces network functionality in virtual components, i.e., software functions running on processing elements; for example, SDN systems implement routing algorithms in software. Shantharama et al [ 73 ] presented an extensive survey on NFV from datacenters to on-chip networks. In their work, they expressed that SDNoC facilitates the integration of interconnection systems at different scales.…”

Section: Literature Reviewmentioning

confidence: 99%

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

et al. 2021

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Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

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“…Several hardware and software strategies can accelerate cloud services [31], [32]. Hardware acceleration can employ custom accelerators, such as FPGA [33] and GPU [34], and dedicated accelerators for service-specific hardware functions, such as DLBoost on Intel Cascade Lake processors [35], which can accelerate deep learning algorithms on both containers and VMs.…”

Section: Related Workmentioning

confidence: 99%

Hardware Acceleration for Container Migration on Resource-Constrained Platforms

et al. 2020

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The computing capabilities of client devices are continuously increasing; at the same time, demands for ultra-low latency (ULL) services are increasing. These ULL services can be provided by migrating some micro-service container computations from the cloud and multi-access edge computing (MEC) to the client devices. The migration of a container image requires compression and decompression, which are computationally demanding. We quantitatively examine the hardware acceleration of container image compression and decompression on a client device. Specifically, we compare the Intel ® Quick Assist Technology (QAT) hardware acceleration with software compression/decompression. For scenarios with a local container image registry (i.e., without network bandwidth constraints), we find that QAT speeds up compression by a factor of over 7 compared to the single-core GZIP software and reduces the CPU core utilization by over 15% for large container images. These QAT benefits come at the expense of Input/Output (IO) memory access bitrates of up to 900 Mbyte/s (while the software compression/decompression does not require IO memory access). For scenarios with a remote container image registry, we find that the container push (compression) time savings increase with the network bandwidth, while the container pull (decompression) time savings level out for moderately high network bandwidths and slightly decrease for a very high network bandwidth. Furthermore, QAT acceleration achieves substantial power consumption reductions for container push compression for low to moderately high network bandwidths. Our evaluation results give reference performance benchmarks of the achievable latencies for container image instantiation and migration with and without hardware acceleration of the compression and decompression of container images.

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Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Cited by 62 publications

References 266 publications

Optimum Functional Splits for Optimizing Energy Consumption in V-RAN

Optimum Functional Splits for Optimizing Energy Consumption in V-RAN

A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Hardware Acceleration for Container Migration on Resource-Constrained Platforms

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