Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D

Lee, B.H.; Mocuta, A.; Bedell, Stephen W.; Chen, H.; Sadana, D. K.; Rim, K.; O’Neil, P.; Mo, R.; Chan, Kuo-Chin; Cabral, C.; Lavoie, C.; Mocuta, D.; Chakravarti, A.; Mitchell, R.; Mezzapelle, J.; Jamin, F.; Sendelbach, Matthew; Kermel, H.; Gribelyuk, M.; Domenicucci, A.; Jenkins, K.A.; Narasimha, S.; Ku, S.H.; Ieong, M.; Yang, Insoon; Leobandung, E.; Agnello, P.; Haensch, Wilfried; Welser, J.J.

doi:10.1109/iedm.2002.1175993

Cited by 19 publications

(7 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The performance benefits of combining strained silicon with an SOI has been demonstrated in a 60 nm gate-length, n-channel MOSFET with ultrathin thermally mixed strained silicon/SiGe on insulator sub- strate (strain-Si on insulator SSOI, SiGe on insulator SGOI). 20-25% device enhancement is demonstrated at short channel length [405]. Hole mobility can also be improved by large amounts of tensile strain.…”

Section: Strained Simentioning

confidence: 93%

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Zhu

Sun

et al. 2011

Progress in Materials Science

134

View full text Add to dashboard Cite

Section: Strained Simentioning

confidence: 93%

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Zhu

Sun

et al. 2011

Progress in Materials Science

134

View full text Add to dashboard Cite

“…Strained silicon (Si) field effect transistors (FETs) have recently been proposed [1][2][3][4][5][6][7][8][9][10]. Their driving capability is superior to that of the pure Si-based FETs.…”

Section: Introductionmentioning

confidence: 99%

Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors

Lee

Chou

2004

J Comput Electron

View full text Add to dashboard Cite

In this paper we numerically examine the electrical characteristics of surrounding-gate strained silicon nanowire field effect transistors (FETs) by changing the radius (R SiGe ) of silicon-germanium (SiGe) wire. Due to the higher electron mobility, the n-type FETs with strained silicon channel films do enhance driving capability (∼8% increment on the drain current) in comparison with the pure Si one. The leakage current and transfer characteristics, the threshold-voltage (V t ), the drain induced barrier height lowering (DIBL), and the gate capacitance (C G ) are estimated with respect to different gate length (L G ), gate bias (V G ), and R SiGe . For short channel effects, such as V t roll-off and DIBL, the surrounding-gate strained silicon nanowire FET sustains similar characteristics with the pure Si one.

show abstract

“…SOI technology has been proposed as the next technology enabling the continuity of Moore's law [1]. The emergent generalization of SOI technology can be seen recently in the literature [2,3].…”

Section: Introductionmentioning

confidence: 99%

A comparison of shielded and conventional on-wafer test-fixture forward coupling on silicon-on-insulator (SOI) substrate

Kaija

Ristolainen

2005

Microw. Opt. Technol. Lett.

View full text Add to dashboard Cite

show abstract

Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D

Cited by 19 publications

References 2 publications

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Silicon-Germanium Structure in Surrounding-Gate Strained Silicon Nanowire Field Effect Transistors

A comparison of shielded and conventional on-wafer test-fixture forward coupling on silicon-on-insulator (SOI) substrate

Contact Info

Product

Resources

About