Performance enhancement of strained-Si MOSFETs fabricated on a chemical-mechanical-polished SiGe substrate

Sugii, Nobuyuki; Hisamoto, D.; Washio, Katsuyoshi; Yokoyama, N.; Kimura, S.

doi:10.1109/ted.2002.805231

Cited by 69 publications

(37 citation statements)

References 13 publications

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“…For the other data plotted on this figure, the technological processes for NMOS fabrication including a GBL were similar and lead to close mobility values [11,45,47]. Our results obtained from Monte Carlo simulation are in accordance with the best experimental mobility enhancements [7,12,13]. …”

Section: Effect Of Strain On Electron Mobilitysupporting

confidence: 81%

“…6 shows a discrepancy between the various experimental results. For instance, for x = 0.30, the electron mobility can be enhanced by ≈ 80% [11] or by 120% [12,13]. These differences can be explained in terms of surface roughness of the strained Si/Si 1-x Ge x .…”

Section: Effect Of Strain On Electron Mobilitymentioning

confidence: 99%

“…Now efforts are made to transfer this advantage in CMOS technology on either bulk or insulating substrate [7][8][9][10]. It has been demonstrated that the effective electron mobility in MOS structures can be substantially enhanced using tensile strained-Si channel grown on SiGe buffer layer [7,11,12,13].…”

Section: Introductionmentioning

confidence: 99%

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Electron effective mobility in strained-Si/Si1−xGex MOS devices using Monte Carlo simulation

Aubry-Fortuna

Dollfus

Galdin‐Retailleau

2005

Solid-State Electronics

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Based on Monte Carlo simulation, we report the study of the inversion layer mobility in n-channel strained Si/ Si 1-x Ge x MOS structures. The influence of the strain in the Si layer and of the doping level is studied. Universal mobility curves µ eff as a function of the effective vertical field E eff are obtained for various state of strain, as well as a fall-off of the mobility in weak inversion regime, which reproduces correctly the experimental trends. We also observe a mobility enhancement up to 120 % for strained Si/ Si 0.70 Ge 0.30 , in accordance with best experimental data. The effect of the strained Si channel thickness is also investigated: when decreasing the thickness, a mobility degradation is observed under low effective field only.

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Section: Effect Of Strain On Electron Mobilitysupporting

confidence: 81%

Section: Effect Of Strain On Electron Mobilitymentioning

confidence: 99%

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Electron effective mobility in strained-Si/Si1−xGex MOS devices using Monte Carlo simulation

Aubry-Fortuna

Dollfus

Galdin‐Retailleau

2005

Solid-State Electronics

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“…Many studies have reported that strain is unequally distributed along the channel induced by a uniaxial or biaxial stressor [1]- [6]. The electrical properties related to strain structure have also been reported to be channel length dependent [8]- [12], [16]- [20]. However, only a few studies have focused on the relationship between channel width and length in terms of comparing the impacts of unstrained and strained devices, particularly with decreasing size.…”

Section: Introductionmentioning

confidence: 99%

Performance Dependence on Width-to-Length Ratio of Si Cap/SiGe Channel MOSFETs

Chang

Lin

2013

IEEE Trans. Electron Devices

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This paper measures the n-and p-MOSFETs fabricated through 65-nm high-k/metal gate CMOSFET process flow. The [110] channels of the Si cap on SiGe with different width (W ) and length (L) ratios were compared with Si-only channels. The results show that a high W-L ratio in the [110] n-channel can alleviate the degradation of biaxial compressive stress. Meanwhile, a low W-L ratio in the p-channel can improve the performance; however, the ratio should at least be below two in this paper. The dominance of the longitudinal or transverse configurations successfully explains this phenomenon because of the reliance of the different levels of piezoresistance coefficient on the channel orientation. The threshold voltage shifts versus the W-L ratio in the p-channel is in agreement with the result. The result is verified by a quantitative current comparison at a high bias in the n-/p-channels between the strained SiGe and Si-only channels, which shows that an extreme W-L ratio in the original biaxially strained SiGe channel can result in longitudinal or transverse strain, thereby leading to different levels of performance degradation/improvement.

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“…This avoids the complexity and cost of thick epitaxial growth 5,6 and chemical mechanical polishing. 7,8 Other, more complex methods such as molecular beam epitaxy, He implantation, 9 and C incorporation at interfaces during growth 10 have been reported for the growth of significantly thin buffer layers. Our technique uses the rapid, but distinct changes in the Ge mole fraction to create multiple Si 1)x Ge x interfaces within the buffer layer.…”

Section: Introductionmentioning

confidence: 99%

Ultra-Thin Si1−x Ge x Dislocation Blocking Layers for Ge/Strained Si CMOS Devices

Joshi

Dey

Chaumont

et al. 2007

Journal of Elec Materi

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We demonstrate ultra-thin (<150 nm) Si 1)x Ge x dislocation blocking layers on Si substrates used for the fabrication of tensile-strained Si N channel metal oxide semiconductor (NMOS) and Ge P channel metal oxide semiconductor (PMOS) devices. These layers were grown using ultra high vacuum chemical vapor deposition (UHVCVD). The Ge mole fraction was varied in rapid, but distinct steps during the epitaxial layer growth. This results in several Si 1)x Ge x interfaces in the epitaxially grown material with significant strain fields at these interfaces. The strain fields enable a dislocation blocking mechanism at the Si 1)x Ge x interfaces on which we were able to deposit very smooth, atomically flat, tensile-strained Si and relaxed Ge layers for the fabrication of high mobility N and P channel metal oxide semiconductor (MOS) devices, respectively. Both N and P channel metal oxide semiconductor field effect transister (MOSFETs) were successfully fabricated using high-k dielectric and metal gates on these layers, demonstrating that this technique of using ultra-thin dislocation blocking layers might be ideal for incorporating high mobility channel materials in a conventional CMOS process.

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Performance enhancement of strained-Si MOSFETs fabricated on a chemical-mechanical-polished SiGe substrate

Cited by 69 publications

References 13 publications

Electron effective mobility in strained-Si/Si1−xGex MOS devices using Monte Carlo simulation

Electron effective mobility in strained-Si/Si1−xGex MOS devices using Monte Carlo simulation

Performance Dependence on Width-to-Length Ratio of Si Cap/SiGe Channel MOSFETs

Ultra-Thin Si1−x Ge x Dislocation Blocking Layers for Ge/Strained Si CMOS Devices

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