Performance Analysis of Gate-All-Around Field Effect Transistor for CMOS Nanoscale Devices

Abstract

This paper explains the performance analysis of Gate-AllAround silicon nanowire with 80nm diameter field effect transistor based CMOS based device utilizing the 45-nm technology. Simulation and analysis of nanowire (NW) CMOS inverter show that there is the reduction of 70% in leakage power and delay minimization of 25% as compared with 180 nm channel length.Gate-All-Aorund (GAA) configuration provides better and low drain induced barrier lowering (DIBL) ~63.3mV/V and competent Subthresold slope ~95mV/V. GAA achieved the better voltage gain of ~10.1 V/V .Static noise margin improved with 400mv. It provides high on drive current ~6mA this is validated that the threshold voltage of GAA field effect transistor. KeywordsGate-All-Around (GAA); silicon nanowire; Drain induced barrier lowering (DIBL); Metal oxide semiconductor field effect transistor (MOSFET)

Effect of radius on various parameters of cylindrical surrounding double-gate (CSDG) MOSFET

“…This is made possible by the dual gate with scaled channels dimension which aid higher electron transportation near the source, this attribute enhance the driving current and gate control. Also, the higher transconductance in the double surrounding gate helps with electrostatic control in the operation [25].…”

Novel Linearly Graded Nanotube Field-Effect Transistors for Improved Analog Performance and Reduced Leakage Current

“…It is also found that inner gate configurations among channel-to-drain or source-tochannel regions provide better performance instead of designing the source to drain configuration [14][15][16]. With such complancies, a perspective focuses on the novel working of different materials choices, structures, configurations, and design technology [17][18][19]. Combining the concepts of literature, in the present work, a Linearly Graded Gate metal with inner gate Nanowire FET(LG-NT-FET) with the inclusion of additions as per suggestions extracted from the literature [20,21].…”

Performance Analysis of Fully-Depleted Silicon-On-Insulator (SOI) G 4 -FET and Gate-All-Around (GAA) MOSFETs

“…The continuous scaling of GAA silicon nanowire Field Effect Transistor (FET) [1], [2] illustrates better control of short channel effect over other structures [3] due to their gate controllability, low leakage, high on-off ratio and carrier transport property [4]. For better SS and DIBL, channel length, channel width, channel height, oxide thickness can be considered as important design parameters [5], [6].…”