Partial scan selection based on dynamic reachability and observability information

Hsiao, Michael S.; Saund, G.S.; Rudnick, E.M.; Patel, J.H.

doi:10.1109/icvd.1998.646598

Cited by 23 publications

(8 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Further comparison of the proposed approach to the ones presented in [12] and [13] is not straightforward because the set of benchmarks used is not the same. ISCAS89 circuits [4], used in [12], were not considered in this work because they are described in a structural fashion.…”

Section: Resultsmentioning

confidence: 98%

“…ISCAS89 circuits [4], used in [12], were not considered in this work because they are described in a structural fashion. Since the proposed approach is based on a behavioral description of the circuits, like in ITC99 benchmarks, we could not use the ISCAS89 benchmarks.…”

Section: Resultsmentioning

confidence: 99%

“…The main drawbacks of the approaches in [12] and [13] are that, in the former, the identification of partial scan flip-flops is strongly dependent on a test generation process external to the flip-flop selection procedure and, in the latter, that the original VHDL description is changed to improve the circuit testability bringing area overhead penalties. In this work, we come out with an alternative to those two approaches.…”

Section: Related Workmentioning

confidence: 99%

“…A high-level variable selection for partial-scan approach is proposed in [12] to improve the testability of digital systems described in VHDL. Authors evaluate changes in the control flow of the VHDL description through the insertion of control variables in deviation statements and loops.…”

Section: Related Workmentioning

confidence: 99%

See 3 more Smart Citations

Using a software testing technique to identify registers for partial scan implementation

Krug

Moraes²,

Lubaszewski

2006

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design

View full text Add to dashboard Cite

Scan design has been widely used to ease test generation process for digital circuits. Although full scan approach results in high fault coverage while reducing ATPG effort, it introduces area and performance overheads that are most times unacceptable. Hence, partial scan is a commonly used technique to improve testability of sequential circuits while respecting design constraints. In this paper, we present a method to select sequential elements (flipflops) to compose a partial scan chain. We use a software engineering technique to identify internal variables or signals of the circuit's behavioral description that have low observability. Experiments demonstrate that our approach achieves a high fault coverage including few flip-flops in the scan chain. Moreover, comparative results show that, for complex circuits, proposed technique is more efficient than some classical methods in selecting flip-flops to compose partial scan.

show abstract

Section: Resultsmentioning

confidence: 98%

Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Using a software testing technique to identify registers for partial scan implementation

Krug

Moraes²,

Lubaszewski

2006

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design

View full text Add to dashboard Cite

show abstract

“…The consequent benefit is potential alleviation of the performance penalty of scan, in addition to other benefits such as test time, data volume and power reduction. The previously proposed techniques in partial scan can be classified mainly into three categories: structure-based techniques that typically involves breaking the cycles and/or reducing scan depth [1,2,3,4,5,6,7,8,9,10,11], testabilitybased techniques that select scan flip-flops based on testability improvements [5,6,12,13,14,15,16,17,18,19,20,21], and test generation-based techniques which intertwine test generation and scan flip-flop selection [22,23,24,25,26,27]. Other partial scan techniques include those driven by layout constraints [5], timing constraints [28], re-timing [2,29], and toggling rate of flip-flops and entropy measures [30].…”

Section: Introductionmentioning

confidence: 99%

Eliminating Performance Penalty of Scan

Sinanoglu

2012

2012 25th International Conference on VLSI Design

View full text Add to dashboard Cite

Stringent performance requirements magnify the performance degradation impact of Design-for-Testability (DfT) techniques. As more aggressive performance optimizations are being employed, resulting in high-performance designs with reduced logic depth, the impact of scan multiplexers is becoming even more magnified. In this work, we propose a scan cell transformation technique that transfers the scan multiplexer delay from the input of the flip-flop to its output, enabling the removal of the scan multiplexer delay off the critical paths. By inserting a few shadow flip-flops properly, the proposed transformation technique retains test development (test data, quality, etc.) and application (test time, power dissipation, etc.) intact, fully complying with the conventional design and test flow. Experimental results justify the efficacy of the proposed techniques in eliminating the performance penalty of scan quickly and cost-effectively, and thus in enhancing functional speed of integrated circuits.

show abstract

Eliminating the Timing Penalty of Scan

Sinanoglu

Agrawal

2013

J Electron Test

View full text Add to dashboard Cite

Partial scan selection based on dynamic reachability and observability information

Cited by 23 publications

References 24 publications

Using a software testing technique to identify registers for partial scan implementation

Using a software testing technique to identify registers for partial scan implementation

Eliminating Performance Penalty of Scan

Eliminating the Timing Penalty of Scan

Contact Info

Product

Resources

About