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Abstract|T est generation using deterministic faultoriented algorithms is highly complex and time-consuming. New approaches are needed to augment the existing techniques, both to reduce execution time and to improve fault coverage. In this work, we describe a genetic algorithm (GA) framew ork for sequential circuit test generation. The GA evolves candidate test vectors and sequences, using a fault simulator to compute the tness of each candidate test. Various GA parameters are studied, including alphabet size, tness function, generation gap, population size, and mutation rate, as well as selection and crossover schemes. High fault coverages were obtained for most of the IS-CAS89 sequential benchmark circuits, and execution times were signicantly lower than in a deterministic test generator in most cases. I IntroductionSimulation-based test generation has been used to avoid the long execution times of deterministic algorithms and to reduce the complexity of the test generator. In particular, in a simulation-based approach, processing occurs in the forward direction only; i.e., no backtracing is required. Therefore, complex component t ypes are more easily handled. As a result, the development time is greatly reduced.Seshu and Freeman [1] rst proposed simulation-based test generation, and several simulation-based test generators have since been developed [2,3,4,5,6,7]. Breuer [2] used a fault simulator to evaluate sets of random vectors and to select the best vector to apply in each time frame. Weighted random pattern generators were interfaced with fault simulators in [3,4,5], and high fault coverages were obtained for combinational circuits. The test generators in [6,7] were also built around fault simulators, but only candidate vectors of Hamming distance one from the previous vector were considered. Specic faults were targeted in [6], with a backtrace step used to select the bit to be ipped. Cost functions calculated during concurrent This research w as supported in part by the Semiconductor Research Corporation under Contract SRC 93-DP-109.fault simulation were used to evaluate candidate vectors in [7]. While development of these random and mutation-based test generators was simplied and test generation time was reduced, the test sets generated were typically much longer than those generated by deterministic test generators.Genetic algorithms (GAs) were rst used as a framework for simulation-based test generation in [8,9], but only combinational circuits were handled in [9]. The CRIS test generator [8] used a logic simulator to evaluate candidate test sequences; consequently the test sets generated often had lower fault coverages than those generated by a deterministic test generator. Furthermore, a heuristic crossover scheme was used to exploit problem-specic knowledge, making it dicult to separate the eects of the GA from the application-specic heuristics used. The simple GA described by Goldberg [10] was applied to the generation of individual test vectors for combinational and sequential circuits in [11]....

This paper presents a new static logic implicationalgorithm. An improved implication procedure that fully takes advantage of the special context of static implication, the iterative method, and set algebra is described. The algorithm discovers at low cost many indirect implications which are not discovered by dynamic learning without tremendous time cost. The experimental results show that a very large number of indirect implications are found by our algorithm. The static implication procedure has many useful applications, one of which is static redundancy identification. Use of the static implications obtained from the algorithm in static redundancy identification for IS-CAS85 combinational circuits resulted in a larger number of redundant faults identified than in previous methods. I IntroductionStatic logic implication, also called static learning[l], is a procedure which performs implications on both value assignments (0 and 1) for all nodes of a circuit. It is often included in the preprocessing phase of test generation and other applications [1]-[6]. For example, it is used in ATPG to avoid repetitive computation of signal assignments and accelerate the test pattern generation. Since the usual direct implications made by forward and backward propagation can be quickly determined during the dynamic learning phase, the emphasis of static learning should be put on indirect implications, those necessary assignments that cannot be found by simple forward and backward signal propagation [2]. Indirect iniplications play a critical role in many processes, such as multi-level logic optimization [4], redundancy identification [7][8], ATPG [2], and logic verification. A vast majority of indirect implications, especially unilateral indirect implications[2], can be easily found in static learning using the contrapositive law, while it is difficult, and sometimes practically impossible, to discover them in dynamic learning. Some 'This research was supported in part by the Semiconductor Research Corporation under contract SRC 96-DP-109, in part by DARPA under contract DABT63-95-C-0069, and by HewlettPackard under an equipment grant.previous work [9] in ATPG also showed that with a complete and efficient preprocessing phase, dynamic calculation of the logical dependencies among nodes is not required to process the vast majority of faults. Therefore, static learning is a very important preprocessing step.A number of papers have dealt with implication procedures [1]-[4][9]-[12]. The learning procedures described in [3] and [5] can discover some indirect implications, but they are not sufficient for identifying large numbers of indirect implications. Rajski and Cox used a 16-value logic algebra and reduction list method to determine necessary assignments [9]. Chakradhar and Agrawal proposed a novel transitive closure based algorithm, which guarantees the identification of all implications of a partial set of node values [lO][ll]. The advantage of the algorithms proposed in [9]-[ll] is that they not only identify necessary va...

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