Parallel algorithms for FPGA placement

Haldar, M.; Nayak, Ameeya Kumar; Choudhary, Alok; Banerjee, P.

doi:10.1145/330855.330988

Cited by 27 publications

(28 citation statements)

References 9 publications

(13 reference statements)

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“…An evaluation of parallel placement algorithms for FPGAs was documented in [11]. The authors attempted two parallelization strategies: First, they parallelized VPR's simulated annealing by allowing parallel swaps on an SGI Origin shared-memory multiprocessor.…”

Section: Prior Workmentioning

confidence: 99%

Hardware-assisted simulated annealing with application for fast FPGA placement

Wrighton¹,

DeHon²

2003

Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays - FPGA '03

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To truly exploit FPGAs for rapid turn-around development and prototyping, placement times must be reduced to seconds; latebound, reconfigurable computing applications may demand placement times as short as microseconds. In this paper, we show how a systolic structure can accelerate placement by assigning one processing element to each possible location for an FPGA LUT from a design netlist. We demonstrate that our technique approaches the same quality point as traditional simulated annealing as measured by a simple linear wirelength metric. Experimental results look ahead to compare quality against VPR's fast placer when considering the minimum channel width required to route as the primary optimization criteria. Preliminary results from an FPGA implementation show the feasibility of accelerating simulated annealing by three orders of magnitude using this approach. This means we can place the largest design in the University of Toronto's "FPGA Placement and Routing Challenge" in around 4ms.

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Section: Prior Workmentioning

confidence: 99%

Hardware-assisted simulated annealing with application for fast FPGA placement

Wrighton¹,

DeHon²

2003

Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium on Field Programmable Gate Arrays - FPGA '03

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“…In this paper, we investigated the speedup achieved using mincut partitioning as opposed to direct partitioning into vertical and horizontal strips [16]. Moreover, our implementation is based on multithreading and run on the same chip rather than on distributed processors in a shared memory network architecture [16].…”

Section: Discussionmentioning

confidence: 99%

“…From an algorithmic point of view, previous work techniques can be classified into move acceleration [13,14] and parallel moves based [15][16][17] solutions. The parallel moves approaches include: (i) techniques using one copy of the main placement problem, (ii) techniques using multiple copies of the main placement problem, and (iii) techniques using placement subproblems of the main placement.…”

Section: International Journal Of Reconfigurable Computingmentioning

confidence: 99%

“…Our solution can be classified as a technique in the (iii) category (using placement region-based subproblems) discussed in the previous section. The main difference (apart from using multithreading) between our implementation and previous region-based parallel solutions [16] is the fast mincut balanced partitioning that we use. This minimizes the number of nets with terminals in different partitions, and therefore, minimizes the amount of dependencies between tasks.…”

Section: Contributionmentioning

confidence: 99%

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Speeding Up FPGA Placement via Partitioning and Multithreading

Ababei

2009

International Journal of Reconfigurable Computing

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One of the current main challenges of the FPGA design flow is the long processing time of the placement and routing algorithms. In this paper, we propose a hybrid parallelization technique of the simulated annealing-based placement algorithm of VPR developed in the work of Betz and Rose (1997). The proposed technique uses balanced region-based partitioning and multithreading. In the first step of this approach placement subproblems are created by partitioning and then processed concurrently by multiple worker threads that are run on multiple cores of the same processor. Our main goal is to investigate the speedup that can be achieved with this simple approach compared to previous approaches that were based on distributed computing. The new hybrid parallel placement algorithm achieves an average speedup of 2.5× using four worker threads, while the total wire length and circuit delay after routing are minimally degraded.

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“…• some form of partitioning/clustering the design into groups of clusters (which we call super-clusters) before running the placer [9], • quickly creating a good initial placement to reduce the iterations required to find the final placement [10], and • using multi-threading techniques that allow the placer to leverage the increased processing power available on multicore processors [11], [2]. Although our long term research objectives include creating a placement algorithm that scales better in performance for multicore processors, the current study focuses on a good placement's final structure in relation to the actual design.…”

Section: Introductionmentioning

confidence: 99%

Finding System-Level Information and Analyzing Its Correlation to FPGA Placement

Gharibian

Shannon

Jamieson

2010

2010 International Conference on Field Programmable Logic and Applications

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Abstract-One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement from a flattened design that no longer contains any high-level information related to the original design hierarchy. Unfortunately, placement is an NP-hard problem and as the size and complexity of designs implemented on FPGAs increases, SA does not scale well to find good solutions in a timely fashion. As modern FPGAs can be used to implement Systems-and Networks-on-Chip, designers are required to spend an increasing amount of time waiting for place and route tools to complete that is not being matched by an increase in the power of computing work stations.In this paper, we investigate if system-level information can be reconstructed from a flattened netlist and evaluate how that information is realized in terms of its locality in the final placement. If there is a strong relationship between good quality placements and system-level information, then it may be possible to divide a large design into smaller components and improve the time needed to create a good quality placement. Our preliminary results suggest that the locality property of the information embedded in the system-level HDL structure (i.e. "module", "always", and "if" statements) is greatly affected by both the designer and the design itself. A reconstructive algorithm, called affinity propagation, is also considered as a possible method of generating a meaningful coarse grain picture of the design.

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Parallel algorithms for FPGA placement

Cited by 27 publications

References 9 publications

Hardware-assisted simulated annealing with application for fast FPGA placement

Hardware-assisted simulated annealing with application for fast FPGA placement

Speeding Up FPGA Placement via Partitioning and Multithreading

Finding System-Level Information and Analyzing Its Correlation to FPGA Placement

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