Speeding Up FPGA Placement via  Partitioning and Multithreading

Ababei, Cristinel

doi:10.1155/2009/514754

Cited by 20 publications

(7 citation statements)

References 27 publications

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“…Using the vendor tools to generate the bitstreams at run-time is also impractical as, depending on circuit-size, this can take hours for one specialized circuit. This is shown in the work of Abadei [4].…”

Section: Dynamic Circuit Specialisationmentioning

confidence: 70%

Data path analysis for dynamic circuit specialisation

Davidson

Stroobandt

2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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Abstract-Dynamic Circuit Specialisation (DCS) is a method that exploits the reconfigurability of modern FPGAs to allow the specialisation of FPGA circuits at run-time. Currently, it is only explored as part of Register-transfer level design. However, at the Register-transfer level (RTL), a large part of the design is already locked in. Therefore, maximally exploiting the opportunities of DCS could require a costly redesign. It would be interesting to already have insight in the opportunities for DCS from the higher abstraction level. Moreover, the general design trend in FPGA design is to work on higher abstraction levels and let tool(s) translate this higher level description to RTL. This paper presents the first profiler that, based on the high-level description of an application, estimates the benefits of an implementation using DCS. This allows a designer to determine much earlier in the design cycle whether or not DCS would be interesting. The highlevel profiling methodology was implemented and tested on a set of PID designs.

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Section: Dynamic Circuit Specialisationmentioning

confidence: 70%

Data path analysis for dynamic circuit specialisation

Davidson

Stroobandt

2014

2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14)

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“…However, to have all the information necessary for this calculation, the complete Xilinx FPGA tool flow has to be run. Placement and routing are the most time-consuming steps in the Xilinx tool flow [Ababei 2009] and are necessary to determine the exact value of t DC S , t orig in Equation (5) and # f rames in the HWICAP T SST calculation. If we want to improve the runtime of the profiler, then avoiding placement and routing will have the most significant impact.…”

Section: T Hw Ic Apmentioning

confidence: 99%

Identification of Dynamic Circuit Specialization Opportunities in RTL Code

Davidson

Vansteenkiste

Heyse

et al. 2015

ACM Trans. Reconfigurable Technol. Syst.

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Dynamic Circuit Specialization (DCS) optimizes a Field-Programmable Gate Array (FPGA) design by assuming a set of its input signals are constant for a reasonable amount of time, leading to a smaller and faster FPGA circuit. When the signals actually change, a new circuit is loaded into the FPGA through runtime reconfiguration. The signals the design is specialized for are called parameters. For certain designs, parameters can be selected so the DCS implementation is both smaller and faster than the original implementation. However, DCS also introduces an overhead that is difficult for the designer to take into account, making it hard to determine whether a design is improved by DCS or not. This article presents extensive results on a profiling methodology that analyses Register-Transfer Level (RTL) implementations of applications to check if DCS would be beneficial. It proposes to use the functional density as a measure for the area efficiency of an implementation, as this measure contains both the overhead and the gains of a DCS implementation. The first step of the methodology is to analyse the dynamic behaviour of signals in the design, to find good parameter candidates. The overhead of DCS is highly dependent on this dynamic behaviour. A second stage calculates the functional density for each candidate and compares it to the functional density of the original design. The profiling methodology resulted in three implementations of a profiling tool, the DCS-RTL profiler. The execution time, accuracy, and the quality of each implementation is assessed based on data from 10 RTL designs. All designs, except for the two 16-bit adaptable Finite Impulse Response (FIR) filters, are analysed in 1 hour or less.

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“…A similar approach is followed by Ababei [2009], in which a mini-cut algorithm divides the placement of the overall netlist to smaller placement problems, so that these problems can be solved in parallel. However, the derived placement quality is degraded.…”

Section: Related Workmentioning

confidence: 99%

Genesis

Diamantopoulos

Siozios

Xydis

et al. 2015

ACM Trans. Embed. Comput. Syst.

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Placement is though as the most time-consuming processes in physical implementation flows for reconfigurable architectures, while it highly affects the quality of derived application implementation, as it has impact on the maximum operating frequency. Throughout this article, we propose a novel placer, based on genetic algorithm, targeting to FPGAs. Rather than relevant approaches, which are executed sequentially, the new placer exhibits inherent parallelism, which can benefit from multicore processors. Experimental results prove the effectiveness of this solution, as it achieves average reduction of execution runtime and application's delay by 67× and 16%, respectively.

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Speeding Up FPGA Placement via Partitioning and Multithreading

Cited by 20 publications

References 27 publications

Data path analysis for dynamic circuit specialisation

Data path analysis for dynamic circuit specialisation

Identification of Dynamic Circuit Specialization Opportunities in RTL Code

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