Page placement in hybrid memory systems

Ramos, Luiz Armando Vidal; Gorbatov, Eugene; Bianchini, Ricardo

doi:10.1145/1995896.1995911

Cited by 341 publications

(255 citation statements)

References 40 publications

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“…Other types of applications may not directly benefit from persistent memory, but can still use BA-NVMs as their working memory (nonvolatile main memory without persistence) to leverage the benefits of large capacity and low stand-by power [45,73]. For example, a large number of recent works aim to fit BA-NVMs as part of main memory in the traditional two-level storage model [19,20,33,45,46,57,72,73,74,91,94]. Several very recent works [38,52,59] envision that BA-NVMs can be simultaneously used as persistent memory and working memory.…”

Section: Introductionmentioning

confidence: 99%

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Zhao

Mutlu²,

Xie

2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Byte-addressable nonvolatile memories promise a new technology, persistent memory, which incorporates desirable attributes from both traditional main memory (byte-addressability and fast interface) and traditional storage (data persistence). To support data persistence, a persistent memory system requires sophisticated data duplication and ordering control for write requests. As a result, applications that manipulate persistent memory (persistent applications) have very different memory access characteristics than traditional (non-persistent) applications, as shown in this paper. Persistent applications introduce heavy write traffic to contiguous memory regions at a memory channel, which cannot concurrently service read and write requests, leading to memory bandwidth underutilization due to low bank-level parallelism, frequent write queue drains, and frequent bus turnarounds between reads and writes. These characteristics undermine the high-performance and fairness offered by conventional memory scheduling schemes designed for non-persistent applications.Our goal in this paper is to design a fair and high-performance memory control scheme for a persistent memory based system that runs both persistent and non-persistent applications. Our proposal, FIRM, consists of three key ideas. First, FIRM categorizes request sources as non-intensive, streaming, random and persistent, and forms batches of requests for each source. Second, FIRM strides persistent memory updates across multiple banks, thereby improving bank-level parallelism and hence memory bandwidth utilization of persistent memory accesses. Third, FIRM schedules read and write request batches from different sources in a manner that minimizes bus turnarounds and write queue drains. Our detailed evaluations show that, compared to five previous memory scheduler designs, FIRM provides significantly higher system performance and fairness.

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Section: Introductionmentioning

confidence: 99%

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Zhao

Mutlu²,

Xie

2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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“…Our HRank implementation manages a flat, exclusive memory system based on hot-cold frames [27,18]. Unlike previous work that tracks recent and adjacent accesses with a multiple-queue (MQ) ranking system [28], we rank frames according to their number of references.…”

Section: Hrankmentioning

confidence: 99%

“…Earlier research to overcome DRAM's power limitations [4,13,17,18,27] proposed heterogeneous memory systems that combine DRAM, for performance, with non-volatile RAM (NVRAM) memory, for power-conscious capacity scaling. NVRAM technologies include phase change memory (PCM) [25] and STT-RAM [2].…”

Section: Introductionmentioning

confidence: 99%

“…The OS manages both memory spaces while the MC supervises page migrations between them. Several policies to migrate pages in this flat design have appeared recently [18,27]. These policies use the following principles: (1) Place performance-critical pages in 1LM and non-performancecritical pages in 2LM, to achieve a combination of overall high performance and low power dissipation; (2) Rank pages based on history of the number of references and access recency.…”

Section: Introductionmentioning

confidence: 99%

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HpMC

Roberts

León

et al. 2015

Proceedings of the 2015 International Symposium on Memory Systems

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DRAM technology faces density and power challenges to increase capacity because of limitations of physical cell design. To overcome these limitations, system designers are exploring alternative solutions that combine DRAM and emerging NVRAM technologies. Previous work on heterogeneous memories focuses, mainly, on two system designs: PCache, a hierarchical, inclusive memory system, and HRank, a flat, non-inclusive memory system. We demonstrate that neither of these designs can universally achieve high performance and energy efficiency across a suite of HPC workloads. In this work, we investigate the impact of a number of multilevel memory designs on the performance, power, and energy consumption of applications. To achieve this goal and overcome the limited number of available tools to study heterogeneous memories, we created HMsim, an infrastructure that enables n-level, heterogeneous memory studies by leveraging existing memory simulators. We, then, propose HpMC, a new memory controller design that combines the best aspects of existing management policies to improve performance and energy. Our energy-aware memory management system dynamically switches between PCache and HRank based on the temporal locality of applications. Our results show that HpMC reduces energy consumption from 13% to 45% compared to PCache and HRank, while providing the same bandwidth and higher capacity than a conventional DRAM system.

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“…In contrast we use both DRAM and persistent memory as separate tiers in a multi-tier memory system, where each tier holds a unique copy of the data that the CPU can access regardless of its location. Dhiman et al [DAR09] and Ramos et al [RGB11] both present hybrid memory systems where PCM is used as an extension of DRAM by modifying the memory controller in order to determine the placement of pages of memory. Our approach instead solves the problem by modifying the page replacement algorithm in the operating system without requiring any hardware modification.…”

Section: Managing Tiered Memory Systems With Multi-clockmentioning

confidence: 99%

Optimizing Main Memory Usage in Modern Computing Systems to Improve Overall System Performance

Campello¹

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Operating Systems use fast, CPU-addressable main memory to maintain an application's temporary data as anonymous data and to cache copies of persistent data stored in slower block-based storage devices. However, the use of this faster memory comes at a high cost. Therefore, several techniques have been implemented to use main memory more efficiently in the literature. In this thesis we introduce three distinct approaches to improve overall system performance by optimizing main memory usage.First, DRAM and host-side caching of file system data are used for speeding up virtual machine performance in today's virtualized data centers. The clustering of VM images that share identical pages, coupled with data deduplication, has the potential to optimize main memory usage, since it provides more opportunity for sharing resources across processes and across different VMs. In our first approach, we study the use of content and semantic similarity metrics and a new algorithm to cluster VM images and place them in hosts where through deduplication we improve main memory usage.Second, while careful VM placement can improve memory usage by eliminating duplicate data, caches in current systems employ complex machinery to manage the cached data. Writing data to a page not present in the file system page cache causes the operating system to synchronously fetch the page into memory, blocking the writing process. In this thesis, we address this limitation with a new approach to managing page writes involving v buffering the written data elsewhere in memory and unblocking the writing process immediately. This buffering allows the system to service file writes faster and with less memory resources.In our last approach, we investigate the use of emerging byte-addressable persistent memory technology to extend main memory as a less costly alternative to exclusively using expensive DRAM. We motivate and build a tiered memory system wherein persistent memory and DRAM co-exist and provide improved application performance at lower cost and power consumption with the goal of placing the right data in the right memory tier at the right time. The proposed approach seamlessly performs page migration across memory tiers as access patterns change and/or to handle tier memory pressure.

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Page placement in hybrid memory systems

Cited by 341 publications

References 40 publications

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

HpMC

Optimizing Main Memory Usage in Modern Computing Systems to Improve Overall System Performance

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