FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Zhao, Jishen; Mutlu, Onur; Xie, Yuan

doi:10.1109/micro.2014.47

Cited by 85 publications

(50 citation statements)

References 74 publications

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“…Principles from BLISS can be employed in both of these contexts to identify and deprioritize interference-causing threads, thereby mitigating interference experienced by vulnerable threads/applications. FIRM [48] proposes request scheduling mechanisms to tackle the problem of heavy write traffic in persistent memory systems. BLISS can be combined with FIRM's write handling mechanisms to achieve better fairness in persistent memory systems.…”

Section: Related Workmentioning

confidence: 99%

BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling

Subramanian

Lee

Seshadri

et al. 2016

IEEE Trans. Parallel Distrib. Syst.

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Abstract-In a multicore system, applications running on different cores interfere at main memory. This inter-application interference degrades overall system performance and unfairly slows down applications. Prior works have developed application-aware memory request schedulers to tackle this problem. State-of-the-art application-aware memory request schedulers prioritize memory requests of applications that are vulnerable to interference, by ranking individual applications based on their memory access characteristics and enforcing a total rank order.In this paper, we observe that state-of-the-art application-aware memory schedulers have two major shortcomings. First, such schedulers trade off hardware complexity in order to achieve high performance or fairness, since ranking applications individually with a total order based on memory access characteristics leads to high hardware cost and complexity. Such complexity could prevent the scheduler from meeting the stringent timing requirements of state-of-the-art DDR protocols. Second, ranking can unfairly slow down applications that are at the bottom of the ranking stack, thereby sometimes leading to high slowdowns and low overall system performance. To overcome these shortcomings, we propose the Blacklisting Memory Scheduler (BLISS), which achieves high system performance and fairness while incurring low hardware cost and complexity. BLISS design is based on two new observations. First, we find that, to mitigate interference, it is sufficient to separate applications into only two groups, one containing applications that are vulnerable to interference and another containing applications that cause interference, instead of ranking individual applications with a total order. Vulnerable-to-interference group is prioritized over the interference-causing group. Second, we show that this grouping can be efficiently performed by simply counting the number of consecutive requests served from each application -an application that has a large number of consecutive requests served is dynamically classified as interference-causing.We evaluate BLISS across a wide variety of workloads and system configurations and compare its performance and hardware complexity (via RTL implementations), with five state-of-the-art memory schedulers. Our evaluations show that BLISS achieves 5% better system performance and 25% better fairness than the best-performing previous memory scheduler while greatly reducing critical path latency and hardware area cost of the memory scheduler (by 79% and 43%, respectively), thereby achieving a good trade-off between performance, fairness and hardware complexity.

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Section: Related Workmentioning

confidence: 99%

BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling

Subramanian

Lee

Seshadri

et al. 2016

IEEE Trans. Parallel Distrib. Syst.

Self Cite

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“…Memory controller designs for persistent memory have been proposed in [2]- [5]. Adding a small DRAM buffer in front of SCM to improve latency and to coalesce writes was proposed in [2].…”

Section: Related Workmentioning

confidence: 99%

“…In contrast the victim cache design here supports concurrent wrap executions and handles log pruning and victim cache space management in an integrated manner. FIRM [5] describes techniques to differentiate persistent and non-persistent memory traffic, and presents scheduling algorithms to maximize system throughput and fairness. Low-level memory scheduling to improve efficiency of persistent memory access was studied in [3].…”

Section: Related Workmentioning

confidence: 99%

Non-Intrusive Persistence with a Backend NVM Controller

Doshi

Giles

et al. 2016

IEEE Comput. Arch. Lett.

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Abstract-By providing instruction-grained access to vast amounts of persistent data with ordinary loads and stores, byte-addressable storage class memory (SCM) has the potential to revolutionize system architecture. We describe a non-intrusive SCM controller for achieving light-weight failure atomicity through back-end operations. Our solution avoids costly software intervention by decoupling isolation and concurrency-driven atomicity from failure atomicity and durability, and does not require changes to the front-end cache hierarchy. Two implementation alternatives -one using a hardware structure, and the other extending memory controller with a firmware managed volatile space, are described.

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“…5) How to design system resources such that they can concurrently handle applications/accesspatterns that manipulate persistent data as well as those that manipulate non-persistent data. (One example recent work [204] tackled the problem of designing effective memory scheduling policies in the presence of these two different types of applications/accesspatterns. )…”

mentioning

confidence: 99%

“…Zhao et al [204] identified this problem and showed that existing memory controllers cannot appropriately handle interference between applications that access persistent data and applications that access volatile data because those that write to persistent data can greatly reduce system performance and fairness due to scheduling policies that do not take into account write requests. They develop a new memory scheduling algorithm that provides a solution to this problem by more fairly handling read and write requests of different applications [204]. Finally, it is critically important to appropriately handle the interference caused by prefetch requests generated by hardware and software prefetchers employed in almost all modern high performance systems [69,174,183].…”

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confidence: 99%

Research Problems and Opportunities in Memory Systems

Mutlu

Subramanian

2014

JSFI

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The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck. At the same time, DRAM technology is experiencing difficult technology scaling challenges that make the maintenance and enhancement of its capacity, energyefficiency, and reliability significantly more costly with conventional techniques.In this article, after describing the demands and challenges faced by the memory system, we examine some promising research and design directions to overcome challenges posed by memory scaling. Specifically, we describe three major new research challenges and solution directions: 1) enabling new DRAM architectures, functions, interfaces, and better integration of the DRAM and the rest of the system (an approach we call system-DRAM co-design), 2) designing a memory system that employs emerging non-volatile memory technologies and takes advantage of multiple different technologies (i.e., hybrid memory systems), 3) providing predictable performance and QoS to applications sharing the memory system (i.e., QoS-aware memory systems). We also briefly describe our ongoing related work in combating scaling challenges of NAND flash memory.Keywords: memory systems, scaling, DRAM, flash, non-volatile memory, QoS, reliability. IntroductionMain memory is a critical component of all computing systems, employed in server, embedded, desktop, mobile and sensor environments. Memory capacity, energy, cost, performance, and management algorithms must scale as we scale the size of the computing system in order to maintain performance growth and enable new applications. Unfortunately, such scaling has become difficult because recent trends in systems, applications, and technology greatly exacerbate the memory system bottleneck. Memory System TrendsIn particular, on the systems/architecture front, energy and power consumption have become key design limiters as the memory system continues to be responsible for a significant fraction of overall system energy/power [112]. More and increasingly heterogeneous processing cores and agents/clients are sharing the memory system [11,36,39,60,78,79,178,181], leading to increasing demand for memory capacity and bandwidth along with a relatively new demand for predictable performance and quality of service (QoS) from the memory system [129,137,176].On the applications front, important applications are usually very data intensive and are becoming increasingly so [17], requiring both real-time and offline manipulation of great amounts of data. For example, next-generation genome sequencing technologies produce massive amounts of sequence data that overwhelms memory storage and bandwidth requirements of today's highend desktop and laptop systems [9,111,186,196,197] yet researchers have the goal of enabling low-cost personalized medicine, which requires even larger amoun...

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FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Cited by 85 publications

References 74 publications

BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling

BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling

Non-Intrusive Persistence with a Backend NVM Controller

Research Problems and Opportunities in Memory Systems

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