PABAM: A Physics-Based Analytical Model to Estimate Bipolar Amplification Effect Induced Collected Charge at Circuit Level

Song, Ruiqiang; Chen, Shuming; Du, Yi; Huang, Pengcheng; Chen, Jianjun; Chi, Yaqing

doi:10.1109/tdmr.2015.2490259

Cited by 14 publications

(8 citation statements)

References 25 publications

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“…However, it significantly reduces the heavy ion-induced sensitive area at high LET value. The PBA effect slightly causes the injection of holes into the N-well at lower LET value due to the perturbation of N-well voltage is not obvious [21][22][23]. The PBA effect does not increase the density of the ionized electron-hole pairs at low LET value and the heavy ion-induced sensitive area does not change at low LET values.…”

Section: Resultsmentioning

confidence: 95%

TAISAM: A Transistor Array-Based Test Method for Characterizing Heavy Ion-Induced Sensitive Areas in Semiconductor Materials

et al. 2022

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The heavy ion-induced sensitive area is an essential parameter for space application integrated circuits. Circuit Designers need it to evaluate and mitigate heavy ion-induced soft errors. However, it is hard to measure this parameter due to the lack of test structures and methods. In this paper, a test method called TAISAM was proposed to measure the heavy ion-induced sensitive area. TAISAM circuits were irradiated under the heavy ions. The measured sensitive areas are 1.75 μm2 and 1.00 μm2 with different LET values. TAISAM circuits are also used to investigate the layout structures that can affect the sensitive area. When the source region of the target transistor is floating, the heavy ion-induced sensitive area decreases by 28.5% for the target PMOS transistor while it increases by more than 28% for the target NMOS transistor. When the well contacts are added, the heavy ion-induced sensitive area decreases by more than 25% for the target PMOS transistor while it remains unchanged for the target NMOS transistor. Experimental results directly validate that the two structures significantly affect the heavy ion-induced sensitive area.

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Section: Resultsmentioning

confidence: 95%

TAISAM: A Transistor Array-Based Test Method for Characterizing Heavy Ion-Induced Sensitive Areas in Semiconductor Materials

et al. 2022

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“…Plenty of experiments have indicated that 3-D mixed-mode TCAD simulation is a useful method to investigate the mechanism of SET [15][16][17][18]. Device and circuit-level mixed-mode simulations are used to obtain the shape, amplitude, and duration of transient pulse generated by the interaction of incident particle and the sensitive transistor in circuits.…”

Section: Simulation Detailsmentioning

confidence: 99%

Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

et al. 2019

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In analog circuit design, the bulks of MOSFETs can be tied to their respective sources to remove body effect. This paper models and analyzes the sensitivity of single-event transients (SETs) in common source (CS) amplifier with bulk tied to source (BTS) in 40 nm twin-well bulk CMOS technology. The simulation results present that the proposed BTS radiation-hardened-by-design (RHBD) technique can reduce charge collection and suppress the SET induced perturbation effectively in various input conditions of the circuit. The detailed analysis shows that the mitigation of SET is primarily due to the forward-bias of bulk potential. This technique is universally applicable in radiation-hardening design for analog circuits with negligible penalty.

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“…In our previous works, TCAD simulation was a useful means to investigate the physical mechanism of single-event effect (SEE) [10,11,12]. In this paper, TCAD simulation was performed to compare the SEU sensitivity of the DICE flip-flop with two layout topologies.…”

Section: Simulation Setupmentioning

confidence: 99%

Impact of adjacent transistors on the SEU sensitivity of DICE flip-flop

Cai

Chen

2017

IEICE Electron. Express

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This paper studies the impact of adjacent transistors on the SEU sensitivity of the DICE flip-flop. We compare the SEU sensitivity of the DICE flip-flop with two different layout topologies. Heavy ion experiment results indicate the separation layout topology can reduce the SEU sensitivity of the DICE flip-flop, both in SEU threshold and SEU cross section. TCAD simulation is used to investigate the mechanisms. Simulation results indicate the higher charge collection capability of adjacent transistors in the separation layout topology is the main reason to reduce the SEU sensitivity.

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PABAM: A Physics-Based Analytical Model to Estimate Bipolar Amplification Effect Induced Collected Charge at Circuit Level

Cited by 14 publications

References 25 publications

TAISAM: A Transistor Array-Based Test Method for Characterizing Heavy Ion-Induced Sensitive Areas in Semiconductor Materials

TAISAM: A Transistor Array-Based Test Method for Characterizing Heavy Ion-Induced Sensitive Areas in Semiconductor Materials

Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

Impact of adjacent transistors on the SEU sensitivity of DICE flip-flop

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