Oxide–nitride–oxide layer optimisation for reliable embedded SONOS memories

Performance and Reliability Features of Advanced Nonvolatile Memories Based on Discrete Traps (Silicon Nanocrystals, SONOS)

“…This is mainly due to the "poor" quality of the so-called default devices used for comparison (stoichiometric nitride). We obtained the best overall results with "standard" nitride [43], [44]. A stoichiometric Si N layer, formed with precursors SiH Cl (DiChloroSilane (DCS)) and NH , showed the best compromise between program/erase efficiency and reliability.…”

“…During erase, holes are injected via direct tunneling from the substrate into the nitride layer. Due to the increased potential of the nitride layer, FN tunneling of electrons from the gate through the top oxide to the nitride layer can occur at the end of the erase process [43], [49]. This results in a saturation caused by a dynamic equilibrium of electron tunneling through the top oxide and hole tunneling through the bottom oxide, as can readily be seen in Fig.…”

“…Results of single cells, 256-b NOR arrays and 26-kb arrays will be discussed. The 26-kb arrays were based on the so-called two-transistor (2 T) memory cell with separate access transistor at the source side of each cell [43].…”

“…In combination with the 2.2-nm bottom oxide, the best results were obtained with 8-nm HTO blocking oxide. Further reduction of the erase saturation can be obtained with the use of a p-type gate instead of a n-type gate [43], [49]. Due to the low concentration of electrons in the p-type gate, the electron tunneling is minimized.…”

“…Inset: normalized V window shift after 10 s as a function of P/E cycles. tunnel oxide, a "thick" top oxide of 5 nm is used [38], [43]. The window closure due to degradation can be prevented to a certain extent with lower erase voltages and shorter erase times, to avoid the self-limiting part of the erase curve.…”