2016
DOI: 10.1109/jlt.2015.2482226
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Overview of the FABULOUS EU Project: Final System Performance Assessment With Discrete Components

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Cited by 8 publications
(9 citation statements)
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“…As DSP has big importance in allowing the FABULOUS architecture to reach the performances previously explained, we moved a step forward to demonstrate that such DSP is reasonably feasible considering the access networks market. In [9] we made an extensive analysis that lead us to conclude that implementing all the processing on a 65 nm CMOS platform would need a 7 mm 2 ASIC and have a power consumption lower than 5 W. In this work we also show that we recently implemented the DSP functions required for the proposed US transmission using commercial FPGA platforms, for both demonstrating real-time operation and the possibility of implementing our system using relatively low sample rates for the DSP. For what concerns the US receiver, the board is equipped as follows:  a two-channels analog to digital converter (ADC) running at 1200 MSps which operates after self-coherent detection and electrical IQ demodulation;  a Virtex 7 VX485T FPGA running on a 300 MHz internal clock.…”
Section: Real-time Operation: Preliminary Resultsmentioning
confidence: 81%
“…As DSP has big importance in allowing the FABULOUS architecture to reach the performances previously explained, we moved a step forward to demonstrate that such DSP is reasonably feasible considering the access networks market. In [9] we made an extensive analysis that lead us to conclude that implementing all the processing on a 65 nm CMOS platform would need a 7 mm 2 ASIC and have a power consumption lower than 5 W. In this work we also show that we recently implemented the DSP functions required for the proposed US transmission using commercial FPGA platforms, for both demonstrating real-time operation and the possibility of implementing our system using relatively low sample rates for the DSP. For what concerns the US receiver, the board is equipped as follows:  a two-channels analog to digital converter (ADC) running at 1200 MSps which operates after self-coherent detection and electrical IQ demodulation;  a Virtex 7 VX485T FPGA running on a 300 MHz internal clock.…”
Section: Real-time Operation: Preliminary Resultsmentioning
confidence: 81%
“…On the other hand, optical-beat-interference (OBI) and carrier-induced Rayleigh back-scattering (RBS), as well as both multiple SOPLs and PNs, could affect the uplink signal [27]- [29]. The optical carrier from multiple-ONUs and LO carrier could interfere with each other due to square-law detection by a PD.…”
Section: A Target Co-pon Multiple Access Optical Link For Verificatimentioning
confidence: 99%
“…In this article, we present the results obtained in the frame of the European FP7-project FABULOUS, dedicated to the development of complex integrated optical circuits for innovative high bit-rate passive optical networks (PONs), fabricated by standard-CMOS technologies [17,18]. The final goal, which is the insertion of the chip in a real passive network, imposes very strict requirements on the loss of the component, which has to be kept as low as possible, as the reflective-PON approach yields a very challenging power budget.…”
Section: Introductionmentioning
confidence: 99%