Overview of high voltage sic power semiconductor devices: development and application

Ji, Shiqi; Zhang, Zheyu; Wang, Fred

doi:10.23919/tems.2017.8086104

Cited by 142 publications

(32 citation statements)

References 54 publications

(69 reference statements)

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“…Gate-source voltage V GS in the segment was increased until drain current of SiC MOSFET reached a load current of 20 A. Different from IGBT, drain current I D of SiC MOSFET in the saturation region increases with drain-source voltage V DS due to its short-channel effect and modest transconductance [34], [35]. In the second segment, where SiC MOSFET was changing from ON-state to fully ON-state.…”

Section: E Gate Charge Characterizationmentioning

confidence: 99%

Fan-Out Panel-Level PCB-Embedded SiC Power MOSFETs Packaging

Hou

Wang²,

Chen

et al. 2020

IEEE J. Emerg. Sel. Topics Power Electron.

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In this article, a novel fan-out panel-level printed circuit board (PCB)-embedded package for phase-leg silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module is presented. Electro-thermomechanical co-design was conducted, and the maximum package parasitic inductance was found to be about 1.24 nH at 100 kHz. Compared with wire-bonded packages, the parasitic inductances of the PCB-embedded package decreased at least by 87.6%. Compared with blind via structure, the thermal resistance of the proposed blind block structure reduced at most by about 26%, and the stress of the SiC MOSFETs decreased by about 45.2%. Then, a novel PCB-embedded packaging process was developed, and three key packaging processes were analyzed. Furthermore, effect of PCB-embedded package on static characterization of SiC MOSFET was analyzed, and it was found that: 1) Output current of PCB-embedded package was decreased under a certain gate-source voltage compared to SiC die; 2) Miller capacitance of SiC MOSFET was increased thanks to parasitic capacitance induced by package; and 3) compared with SiC die, nonflat miller plateau of the PCB-embedded package extends, and as drain-source voltage increases, the nonflat miller plateau extends. Lastly, switching characteristics of the PCB-embedded package and TO-247 package were compared. The results show that the PCB-embedded package has smaller parasitic inductances.

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Section: E Gate Charge Characterizationmentioning

confidence: 99%

Fan-Out Panel-Level PCB-Embedded SiC Power MOSFETs Packaging

Hou

Wang²,

Chen

et al. 2020

IEEE J. Emerg. Sel. Topics Power Electron.

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“…where ω s is the angular frequency of the grid voltage, and all other symbols are consistent with those used in Equations 2and (3). The corresponding relationships of all the variables between the d-q domain and the single-phase circuit domain are the following:…”

Section: Training Neural Network Controllermentioning

confidence: 99%

“…However, the voltage ratings of the currently available power electronic devices are still not sufficient for medium and high voltage grid applications. For example, a 6.5 kV rated device is currently available in the market while the 10 kV rated SiC IGBT and MOSFET are still under development of the research facilities [3]. Hence, the conventional two-level design of the converter is not feasible for medium to high voltage applications.…”

Section: Introductionmentioning

confidence: 99%

Novel Neural Control of Single-Phase Grid-Tied Multilevel Inverters for Better Harmonics Reduction

Hadi

et al. 2018

Electronics

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A single-phase Cascaded H-Bridge (CHB) grid-tied multilevel inverter is introduced with a detailed discussion of the proposed novel neural controller for better efficiency and power quality in the integration of renewable sources. An LCL (inductor-capacitor-inductor) filter is used in the multilevel inverter system to achieve better harmonic attenuation. The proposed Neural Network (NN) controller performs the inner current control and tracks the references generated from the outer loop to satisfy the requirements of voltage or power control. Two multicarrier-based Pulse Width Modulation (PWM) techniques (phase-shifted modulation and level-shifted modulation) are adopted in the development of the simulation model to drive the multilevel inverter system for the evaluation of the neural control technique. Simulations are carried out to demonstrate the effectiveness and efficient outcomes of the proposed neural network controller for grid-tied multilevel inverters. The advantages of the proposed neural control include a faster response speed and fewer oscillations compared with the conventional Proportional Integral (PI) controller based vector control strategy. In particular, the neural network control technique provides better harmonics reduction ability.

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“…For IGBT devices this feedback voltage is not an issue as its switching speed is slower, and the supply turn-off voltage is typically low (≤ −8 ) . Whereas for SiC devices, the faster switching speed leads to a much large di/dt and dv/dt [20]. Meanwhile, as the maximum allowable negative voltage remains a challenge in the SiC technology, it also needs a higher turn-off voltage compared to Si-based power device [21,22].…”

Section: Introductionmentioning

confidence: 99%