Over-60-GHz design technology for an SCFL dynamic frequency divider using InP-based HEMTs

Umeda, Yohtaro; Osafune, K.; Enoki, T.; Yokoyama, Haruki; Ishii, Y.; Imamura, Yoshihiro

doi:10.1109/22.709458

Cited by 12 publications

(6 citation statements)

References 18 publications

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“…Basically, frequency dividers (FDs) can be categorized in two types: digital and analog. The flip-flop-based digital FDs [1], [2] characterize large locking ranges, but generally operate at low frequency band, and suffer from the circuit complexity and high DC power consumptions. Analog one, including regenerative (Miller) [3], [4] and injection locked FDs [5], [6], can operate at very high frequencies and, can be implemented with a few active elements, thus featuring low DC power consumptions.…”

Section: Introductionmentioning

confidence: 99%

A Ka-band frequency divider with high division ratio and low power consumption

Xue

2008

2008 Asia-Pacific Microwave Conference

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IntroductionMicrowave/millimeter-wave communication systems such as wireless local area network and mobile satellite communication systems are rapidly expanding. Among these systems, the essential components are the signal sources. Generally, two approaches can implement such a source. One is the use of a high-quality low-frequency source and then, multi-plying it to the desired frequency. Another is directly designing a microwave/millimeter-wave local oscillator that features power and cost efficiency. For such a local oscillator, the basic issue includes stabilizing the free-running frequencies. Up to now, several techniques, such as using dielectric resonators, cavity resonators and phase-locked loops, have been reported. Using phase-locked loops, as compared to the other two methods, is the planar layout and compact size as well as easily compatible with MMIC.However, low-cost phase-locked loops are commercially available below C-band, i.e. lower than 4GHz. Therefore, a microwave/millimeter-wave frequency divider is always required that acts as a prescaler in a frequency synthesizer. Basically, frequency dividers (FDs) can be categorized in two types: digital and analog. The flip-flop-based digital FDs [1], [2] characterize large locking ranges, but generally operate at low frequency band, and suffer from the circuit complexity and high DC power consumptions. Analog one, including regenerative (Miller) [3], [4] and injection locked FDs [5], [6], can operate at very high frequencies and, can be implemented with a few active elements, thus featuring low DC power consumptions. In this study, an injection locked Ka-band FD is developed. The studied FD enables a very high-order division ratio (up to 9 using only one active element) to be practically implemented, at the same time, achieving an acceptable locking range. The design of such an FD is studied in the paper. For demonstration purpose, an FD is fabricated and measured. Experimental results indicate that with the fundamental oscillating frequency of 3 GHz of the oscillator, a locking range of 180 MHz around 27 GHz is achieved under a small DC power consumption of 12 mW. Meanwhile, the minimum input RF power where the divider starts to operate is less than -20 dBm, demonstrating high input sensitivity. Fig. 1 is the schematic diagram of the proposed FD, which constitutes a high-pass filter (HPF), an oscillator and a low-pass filter (LPF) together with a coupling component. The basic operation principles of the FD can be formulated as follows: a high frequency input or injection signal is applied to the input port. After passing through the HPF, it is coupled to the oscillator. This high frequency is close to some harmonic components of the oscillator and due to the frequency entrainment, the harmonic component that is adjacent to the injection frequency is synchronized by the injection signal. Therefore, the oscillator is stabilized by called super-harmonic injection locking. The stabilized frequency is further filtered out by the LPF. Then, a low frequency ...

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Section: Introductionmentioning

confidence: 99%

A Ka-band frequency divider with high division ratio and low power consumption

Xue

2008

2008 Asia-Pacific Microwave Conference

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“…In these applications, maximum operating speed is often of more concern than power consumption, and emittercoupled logic families (ECL, CML, MCML) are used to exploit the advantages of the di erential topology in terms of speed, symmetry and CMRR [1,2]. Very high speed circuits are commonly designed in III-V ÿeld-e ect transistor technologies (GaAs or InP HEMTs), and SCFL logic is used to implement digital functions [3,4].…”

Section: Introductionmentioning

confidence: 99%

Analytic transient solution of SCFL logic gates

Bersani¹,

Centurelli²,

Fontana³

et al. 2005

Int. J. Circ. Theor. Appl.

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In this paper we propose the analytical solution of switching transients for SCFL logic gates. The analysis of an SCFL logic gate is carried out without linearization and can be brought back to multiple analyses of a basic cell, given by a differential pair with switching input voltages and a variable tail current, to take the effect of series-gating into account. The differential equation for this cell is a Riccati equation, if a quadratic current-voltage relationship is used for the transistors, and it can be solved by the infinite power series method, in case of polynomial input signals. An algorithm is proposed to analyse the full transient of a complex SCFL gate. This provides a closed form expression for transient signals in terms of circuit and device parameters, that can be used for symbolic analysis or fast time-domain numerical simulation. Some case studies are presented for SCFL gates using OMMIC ED02AH technology, and a good agreement between the proposed model and SPICE simulations using complex device models is obtained. Copyright (c) 2005 John Wiley & Sons, Ltd

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“…The limited bandwidth of dynamic dividers is a drawback but poses no problem in many applications which require divider operation only in a specific frequency range. Dynamic dividers manufactured in III-V-technologies and, recently, in SiGe technology achieve maximum operating frequencies of 60GHz to 75GHz [1,2,3]. However, most of these circuits operate over relatively narrow bandwidths of less than one octave.…”

Section: Infineon Technologies Ag Corporate Research Munich Germanymentioning

confidence: 99%

A 79 GHz dynamic frequency divider in SiGe bipolar technology

Knapp

Meister²,

Wurzer³

et al.

2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)

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Conventional static frequency dividers use master-slave flipflops to achieve frequency division. They allow broadband operation down to DC as long as the slew rate of the input signal is high enough. Their upper frequency, however, is limited by the gate delay τ D to a value of approximately 1/(2 τ D ). Significantly higher operating frequencies can be achieved by dynamic frequency dividers. The limited bandwidth of dynamic dividers is a drawback but poses no problem in many applications which require divider operation only in a specific frequency range. Dynamic dividers manufactured in III-V-technologies and, recently, in SiGe technology achieve maximum operating frequencies of 60GHz to 75GHz [1,2,3]. However, most of these circuits operate over relatively narrow bandwidths of less than one octave. This regenerative frequency divider exploits the high-speed potential of SiGe technologies to combine high maximum frequency with operation over wide frequency range. Figure 12.7.1 shows the basic block diagram for regenerative frequency division [4]. The circuit consists of a mixer, a low-pass filter, and an amplifier. The output signal of the amplifier serves as local oscillator (LO) signal for the mixer. Assuming an input frequency f IN and an LO frequency f OUT , the mixer output signal will contain the frequencies f IN ± f OUT . Only the component f IN -f OUT can pass the low-pass filter and stable operation is possible under the condition f IN -f OUT = f OUT . This leads to the desired divide-by-two function with f OUT = f IN / 2. The maximum operating frequency of this divider type is limited by the frequency response of the feedback loop. At high frequencies the loop gain becomes insufficient for divider operation. The lower limit for the input frequency is reached if the low-pass filter no longer suppresses the frequency component of 3f IN / 2 occurring at the mixer output. The obtainable ratio of f IN,max /f IN,min is approximately three. By using an active mixer the basic circuit shown in Figure 12.7.1 can be further simplified. Since the required gain is provided by the mixer, no additional amplifier is necessary. Moreover, the low-pass filter can also be omitted because of the inherent low-pass characteristics of the mixer frequency response. Figure 12.7.2 shows the block diagram of the dynamic frequency divider circuit. It contains an active double-balanced mixer performing the regenerative frequency division and an output buffer/ limiter. This limiter stage is necessary to keep the output amplitude of the divider independent of the applied input signal level. Figure 12.7.3 shows the circuit diagram of the regenerative divider containing the balanced mixer. The input signal is applied to one of the mixer ports, whereas the mixer output is connected to the second mixer input via three cascaded emitter followers. These emitter followers provide the necessary level shifting and help to optimize the frequency response of the feedback loop. The output buffer is connected to the second emitter follower stage....

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Over-60-GHz design technology for an SCFL dynamic frequency divider using InP-based HEMTs

Cited by 12 publications

References 18 publications

A Ka-band frequency divider with high division ratio and low power consumption

A Ka-band frequency divider with high division ratio and low power consumption

Analytic transient solution of SCFL logic gates

A 79 GHz dynamic frequency divider in SiGe bipolar technology

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