A Ka-band frequency divider with high division ratio and low power consumption

Abstract

IntroductionMicrowave/millimeter-wave communication systems such as wireless local area network and mobile satellite communication systems are rapidly expanding. Among these systems, the essential components are the signal sources. Generally, two approaches can implement such a source. One is the use of a high-quality low-frequency source and then, multi-plying it to the desired frequency. Another is directly designing a microwave/millimeter-wave local oscillator that features power and cost efficiency. For such a local oscillator, the basic issue includes stabilizing the free-running frequencies. Up to now, several techniques, such as using dielectric resonators, cavity resonators and phase-locked loops, have been reported. Using phase-locked loops, as compared to the other two methods, is the planar layout and compact size as well as easily compatible with MMIC.However, low-cost phase-locked loops are commercially available below C-band, i.e. lower than 4GHz. Therefore, a microwave/millimeter-wave frequency divider is always required that acts as a prescaler in a frequency synthesizer. Basically, frequency dividers (FDs) can be categorized in two types: digital and analog. The flip-flop-based digital FDs [1], [2] characterize large locking ranges, but generally operate at low frequency band, and suffer from the circuit complexity and high DC power consumptions. Analog one, including regenerative (Miller) [3], [4] and injection locked FDs [5], [6], can operate at very high frequencies and, can be implemented with a few active elements, thus featuring low DC power consumptions. In this study, an injection locked Ka-band FD is developed. The studied FD enables a very high-order division ratio (up to 9 using only one active element) to be practically implemented, at the same time, achieving an acceptable locking range. The design of such an FD is studied in the paper. For demonstration purpose, an FD is fabricated and measured. Experimental results indicate that with the fundamental oscillating frequency of 3 GHz of the oscillator, a locking range of 180 MHz around 27 GHz is achieved under a small DC power consumption of 12 mW. Meanwhile, the minimum input RF power where the divider starts to operate is less than -20 dBm, demonstrating high input sensitivity. Fig. 1 is the schematic diagram of the proposed FD, which constitutes a high-pass filter (HPF), an oscillator and a low-pass filter (LPF) together with a coupling component. The basic operation principles of the FD can be formulated as follows: a high frequency input or injection signal is applied to the input port. After passing through the HPF, it is coupled to the oscillator. This high frequency is close to some harmonic components of the oscillator and due to the frequency entrainment, the harmonic component that is adjacent to the injection frequency is synchronized by the injection signal. Therefore, the oscillator is stabilized by called super-harmonic injection locking. The stabilized frequency is further filtered out by the LPF. Then, a low frequency ...