Over-10&amp;#x00D7;-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme

Tanakamaru, Shuhei; Yanagihara, Yuki; Takeuchi, Ken

doi:10.1109/isscc.2012.6177074

Cited by 23 publications

(17 citation statements)

References 4 publications

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“…The strategy will be stopped when the cycles of LSB page refresh operation reach the per-setting limits, and then the data should be labeled as failed. Read disturbance (RD) and word line program disturbance (WPD) based retention error recovery scheme has also been reported [8][9][10][11].…”

Section: Proposed Retention Error Recovery Schemementioning

confidence: 99%

“…In RD based scheme [8][9][10], all LSB and MSB pages are read out sequentially and all cells are biased in read status as shown in Figure 11(a). The voltage between CG and channel induces read disturbance (RD) and achieves extra floating gate electron re-injection.…”

Section: Proposed Retention Error Recovery Schemementioning

confidence: 99%

“…However, high retention error rate induces a trend of stronger ECC deployed in storage system, with higher hardware overhead and spare bits cost. Currently, retention error recovery schemes are proposed to overcome the high retention error rate problem of MLC NAND flash memories [8][9][10][11]. In these schemes, floating gate electron leakage during retention can be compensated by electron re-injection.…”

Section: Introductionmentioning

confidence: 99%

“…In these schemes, floating gate electron leakage during retention can be compensated by electron re-injection. Electron re-injection is realized by either read disturbance (RD) [8][9][10] or word line program disturbance (WPD) [11]. WPD based scheme presents higher recovery efficiency than RD based scheme [11].…”

Section: Introductionmentioning

confidence: 99%

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LSB page refresh based retention error recovery scheme for MLC NAND Flash

Liu

Pan

et al. 2016

Sci. China Inf. Sci.

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NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell (MLC) technology. High retention error rate in highly program/erase (P/E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit (LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Comparing with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.

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Section: Proposed Retention Error Recovery Schemementioning

confidence: 99%

Section: Proposed Retention Error Recovery Schemementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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LSB page refresh based retention error recovery scheme for MLC NAND Flash

Liu

Pan

et al. 2016

Sci. China Inf. Sci.

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“…To improve the reliability of NAND Flash memory based solid-state drives (SSDs), error-prediction LDPC (EP-LDPC) has been proposed for multi-level-cell (MLC) NAND Flash memory (Tanakamaru et al, 2012(Tanakamaru et al, , 2013, which is effective for long retention times. However, EP-LDPC is not as effective for triple-level cell (TLC) NAND Flash memory, because TLC NAND Flash has higher error rates and is more sensitive to program-disturb error.…”

Section: Introductionmentioning

confidence: 99%

Advanced error-prediction LDPC with temperature compensation for highly reliable SSDs

Tokutomi

Tanakamaru

Iwasaki

et al. 2015

Solid-State Electronics

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a b s t r a c tTo improve the reliability of NAND Flash memory based solid-state drives (SSDs), error-prediction LDPC (EP-LDPC) has been proposed for multi-level-cell (MLC) NAND Flash memory (Tanakamaru et al., 2012(Tanakamaru et al., , 2013, which is effective for long retention times. However, EP-LDPC is not as effective for triple-level cell (TLC) NAND Flash memory, because TLC NAND Flash has higher error rates and is more sensitive to program-disturb error. Therefore, advanced error-prediction LDPC (AEP-LDPC) has been proposed for TLC NAND Flash memory (Tokutomi et al., 2014). AEP-LDPC can correct errors more accurately by precisely describing the error phenomena. In this paper, the effects of AEP-LDPC are investigated in a 2Ânm TLC NAND Flash memory with temperature characterization. Compared with LDPC-with-BER-only, the SSD's data-retention time is increased by 3.4Â and 9.5Â at room-temperature (RT) and 85°C, respectively. Similarly, the acceptable BER is increased by 1.8Â and 2.3Â, respectively. Moreover, AEP-LDPC can correct errors with pre-determined tables made at higher temperatures to shorten the measurement time before shipping. Furthermore, it is found that one table can cover behavior over a range of temperatures in AEP-LDPC. As a result, the total table size can be reduced to 777 kBytes, which makes this approach more practical.

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Flash Signal Processing and NAND/ReRAM SSD

Takeuchi

2012

Inside Solid State Drives (SSDs)

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Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme

Cited by 23 publications

References 4 publications

LSB page refresh based retention error recovery scheme for MLC NAND Flash

LSB page refresh based retention error recovery scheme for MLC NAND Flash

Advanced error-prediction LDPC with temperature compensation for highly reliable SSDs

Flash Signal Processing and NAND/ReRAM SSD

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