High-resolution hard X-ray grating-based imaging method with conventional X-ray sources provides attenuation, refraction and scattering information synchronously, and it is regarded as the next-generation X-ray imaging technology for medical and industrial applications. In this letter, a large phase-stepping approach with at least one order of magnitude lower resolution of the movement is presented to equivalently substitute the current high-positioning-resolution phase-stepping approach. Both the theoretical deduction and actual experiment prove that the new approach is available to relax the requirement of high positioning resolution and strict circumstances so as to benefit the future commercial applications of the grating-based multiple-information imaging technology.

the total ionizing dose (TID) radiation response of a flash memory circuit including high voltage (HV) periphery was studied. We show that functional failure of the charge pumps (CP) is mostly caused by an increased load current, due to radiation induced leakage current in the HV pass transistors. This leads to a failure to program/erase the array in turn.

NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell (MLC) technology. High retention error rate in highly program/erase (P/E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit (LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Comparing with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.

Abstract. (17664, 16512) LDPC code is simulated under AWGN channel. The simulation is led on FPGA platform, with Layered Normalized BP-Based decoding algorithm. The shifting of measurement point is under consideration, where the soft information for decoding is inaccurate. LDPC performance under different situations are compared, and performance decreased rapidly with measurement point shifted. The related research results may provide a key basis for LDPC application in NAND Flash controller.

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