LSB page refresh based retention error recovery scheme for MLC NAND Flash

Abstract

NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell (MLC) technology. High retention error rate in highly program/erase (P/E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit (LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Comparing with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.

Modeling of program Vth distribution for 3-D TLC NAND flash memory

“…Despite the several advantages of 3-D NAND flash memory, its reliability degrades with the continued scaling down and introduction of multi-level cell (MLC) and triple-level cell (TLC) NAND flash memory technologies [13,14]. In particular, the transition from 2-D NAND flash memory to 3-D NAND flash memory has been raising many new challenges [15].…”