Optimizing matrix-matrix multiplication on intel’s advanced vector extensions multicore processor

Hemeida, Ashraf Mohamed; Hassan, Somaia Awad; Alkhalaf, Salem; Mahmoud, Mountasser M.M.; Saber, Mahmoud A.; Bahaa-Eldin, Ayman M.; Senjyu, Tomonobu; Alayed, Abdullah H.

doi:10.1016/j.asej.2020.01.003

Cited by 9 publications

(4 citation statements)

References 12 publications

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“…Robust performance benchmarking is critical for the evaluation of vector extensions. While there is extensive performance evaluation of matrix multiplication on vector extensions for Intel architectures 25,26,27 , to the best of our knowledge, similar studies do not exist for the PowerPC or Arm platforms. Moreover, the introduction of matrix engines is recent in all platforms and therefore only simulated or theorized performance estimates exist for AMX, SVE, or MMA 28,24 .…”

Section: Related Workmentioning

confidence: 99%

Fast matrix multiplication via compiler‐only layered data reorganization and intrinsic lowering

et al. 2023

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The resurgence of machine learning has increased the demand for high-performance basic linear algebra subroutines (BLAS), which have long depended on libraries to achieve peak performance on commodity hardware. High-performance BLAS implementations rely on a layered approach that consists of tiling and packing layers -for data (re)organization -and micro kernels that perform the actual computations. The algorithm for the tiling and packing layers is target independent but is parameterized to the memory hierarchy and register-file size. The creation of high-performance micro kernels requires significant development effort to write tailored assembly code for each architecture. This hand optimization task is complicated by the recent introduction of matrix engines by IBM ® 's POWER10 ™ (Matrix Multiply Assist -MMA), Intel ® (Advanced Matrix eXtensions -AMX), and Arm ® (Matrix Extensions -ME) to deliver high-performance matrix operations. This paper presents a compiler-only alternative to the use of high-performance libraries by incorporating, to the best of our knowledge and for the first time, the automatic generation of the layered approach into LLVM, a production compiler. Modular design of the algorithm, such as the use of LLVM's matrix-multiply intrinsic for a clear interface between the tiling and packing layers and the micro kernel, makes it easy to retarget the code generation to multiple accelerators. The parameterization of the tiling and packing layers is demonstrated in the generation of code for the MMA unit on IBM's POWER10. This paper also describes an algorithm that lowers the matrix-multiply intrinsic to the MMA unit. The use of intrinsics enables a comprehensive performance study. In processors without hardware matrix engines, the tiling and packing delivers performance up to 22× (Intel) -for small matrices -and more than 6× (POWER9) -for large matrices -faster than PLuTo, a widely used polyhedral optimizer. The performance also approaches high-performance libraries and is only 34% slower than OpenBLAS and on-par with Eigen for large matrices. With MMA in POWER10 this solution is, for large matrices, over 2.6× faster the vector-extension solution, matches Eigen performance, and achieves up to 96% of BLAS peak performance.

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Section: Related Workmentioning

confidence: 99%

Fast matrix multiplication via compiler‐only layered data reorganization and intrinsic lowering

et al. 2023

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“…They investigated various vectorization options and available compilers to investigate the impacts on the performances of different algorithms. The authors of [9] explored the optimization of matrix multiplication. The other general concept is sorting, a fast vectorized implementation presented in the paper [10].…”

Section: Introductionmentioning

confidence: 99%

Acceleration of Particle Swarm Optimization with AVX Instructions

Šafařík

Snášel

2023

Applied Sciences

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Parallel implementations of algorithms are usually compared with single-core CPU performance. The advantage of multicore vector processors decreases the performance gap between GPU and CPU computation, as shown in many recent pieces of research. With the AVX-512 instruction set, there will be another performance boost for CPU computations. The availability of parallel code running on CPUs made them much easier and more accessible than GPUs. This article compares the performances of parallel implementations of the particle swarm optimization algorithm. The code was written in C++, and we used various techniques to obtain parallel execution through Advanced Vector Extensions. We present the performance on various benchmark functions and different problem configurations. The article describes and compares the performance boost gained from parallel execution on CPU, along with advantages and disadvantages of parallelization techniques.

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“…With the explosive growth of data quantity and high-flux/high-performance computing requiring urgent, a single chip tends to integrate multiple processor cores [ 1 – 3 ]. There is a need for a large amount of data communication within the kernel; as is often the case, the kernel passes through the bus routes between mutual connections, but this bus connection mode needs to manage the clock synchronization [ 4 ].…”

Section: Introductionmentioning

confidence: 99%

Modeling and Performance Analysis of a Fault-Tolerant 3D Photonic Network-on-Chip Based on Hybrid Photonics–Plasmonics

Zhixun

et al. 2022

Computational Intelligence and Neuroscience

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The performance of electro-optic modulators and optical routers and their routing algorithms are the key factors affecting the performance of networks on optical chips. This paper improves the mesh 3-dimensional photonic network-on-chip (3D-PNoC) topology. An SPP hybrid silicon-based electro-optic modulator and an improved fault-tolerant SPP router are used to improve the performance of the network on an optical chip. SPP switching and SPP MRR are combined to form a fault-tolerant SPP router. On this basis, an improved genetic optimization routing algorithm is implemented on the improved mesh 3D PNoC topology, which completes the data exchange of the IP core of the network on the optical chip. Compared with the case of traditional optoelectronic devices, the performance of on-chip optical networks can be improved effectively. The simulation results show that upon the application of the improved genetic optimization routing algorithm to the improved mesh 3D PNoC topology, the average end-to-end delay is reduced by 32.9%, the throughput rate is increased by 28.5%, and the system power consumption is reduced by 27.6%. On the other hand, the average insertion loss and noise of optical routers are increased by 2.94 dB and 2.95 dB, respectively.

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Optimizing matrix-matrix multiplication on intel’s advanced vector extensions multicore processor

Cited by 9 publications

References 12 publications

Fast matrix multiplication via compiler‐only layered data reorganization and intrinsic lowering

Fast matrix multiplication via compiler‐only layered data reorganization and intrinsic lowering

Acceleration of Particle Swarm Optimization with AVX Instructions

Modeling and Performance Analysis of a Fault-Tolerant 3D Photonic Network-on-Chip Based on Hybrid Photonics–Plasmonics

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