Modeling and Performance Analysis of a Fault-Tolerant 3D Photonic Network-on-Chip Based on Hybrid Photonics–Plasmonics

Abstract

The performance of electro-optic modulators and optical routers and their routing algorithms are the key factors affecting the performance of networks on optical chips. This paper improves the mesh 3-dimensional photonic network-on-chip (3D-PNoC) topology. An SPP hybrid silicon-based electro-optic modulator and an improved fault-tolerant SPP router are used to improve the performance of the network on an optical chip. SPP switching and SPP MRR are combined to form a fault-tolerant SPP router. On this basis, an improved genetic optimization routing algorithm is implemented on the improved mesh 3D PNoC topology, which completes the data exchange of the IP core of the network on the optical chip. Compared with the case of traditional optoelectronic devices, the performance of on-chip optical networks can be improved effectively. The simulation results show that upon the application of the improved genetic optimization routing algorithm to the improved mesh 3D PNoC topology, the average end-to-end delay is reduced by 32.9%, the throughput rate is increased by 28.5%, and the system power consumption is reduced by 27.6%. On the other hand, the average insertion loss and noise of optical routers are increased by 2.94 dB and 2.95 dB, respectively.