Optimizing Circuit Performance and ESD Protection for High-Speed Differential I/Os

Abstract

Impact of ESD protection devices on circuit operation is very important in gigahertz applications. In this paper, the impact of different ESD protection methodologies on CML drivers is discussed. ESD protection is provided using MOSFET and SCR devices. Study of the interaction between driver and ESD protection circuit shows that jitter is very sensitive to parasitics of ESD protection circuits. Furthermore, an analysis shows that substrate-triggering has less impact on jitter compared to gate-coupling.

ESD protection design for I/O libraries in advanced CMOS technologies

“…As a result, an ESD protection circuit can degrade both frequency response and linearity performance of the main circuit. Table 5-1 shows the maximum swing, rise time and jitter for different ESD capacitance values of the 4 Gb/s two stage CML driver that was designed in 0.13 lm CMOS process [30]. Differential output swing of the driver was targeted to be at least 800 mV with rise/fall time of less than 150 ps.…”

ESD protection circuit for 8.5Gbps I/Os in 90nm CMOS technology

“…Majority of these publications are targeting RF circuits, mainly low noise amplifiers. There are also a few papers on the interaction between high performance circuits and ESD protection devices [1], [2], [3]. In [1] the impact of ESD protection circuits on distortion of analog to digital converters is investigated.…”

“…In [1] the impact of ESD protection circuits on distortion of analog to digital converters is investigated. A comparison between MOS-based and SCRbased ESD devices on current mode logic (CML) drivers is presented in [2]. In [3] an ESD protection circuit is designed for a 2.5GHz receiver.…”