ESD protection design for I/O libraries in advanced CMOS technologies

Semenov, O.; Somov, S.

doi:10.1016/j.sse.2008.05.008

Cited by 12 publications

(1 citation statement)

References 21 publications

(35 reference statements)

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“…8. These input diodes are needed, especially in deep-submicron technologies where the prototype can be destroyed easily due to ESD.They are designed for this purpose following a layout strategy for high-frequency I/O pads proposed in [9]. They have minimum size for a reduced parasitic capacitance (72 fF), thus protecting in an efficient way but with no visible effect on the frequency response.…”

Section: Resultsmentioning

confidence: 99%

2.5 Gb/s CMOS preamplifier for low-cost fiber-optic receivers

Pozo

Serdijn

Otín

et al. 2010

Analog Integr Circ Sig Process

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This paper reports an optical preamplifier intended for low-cost fiber-optic receivers. The preamplifier is based on a resistive shunt-feedback topology, is poweroptimized and employs two different frequency compensation techniques, phantom zeros and shunt-peaking. The circuit is designed in a 1.8 V 0.18 lm CMOS technology. Experimental results report a transresistance of 58 dBX and a bandwidth of 1.5 GHz, respectively. Eye diagrams obtained at 2.5 Gb/s show a total jitter of 18 ps and a bit error rate (BER) of 10 -12 when the input current amplitude (I in ) is equal to or higher than 8.5 lA. Higher bit rates up to 3 Gb/s also have been tested achieving a BER of 10 -12 when I in C9.5 lA. The power consumption and die active area are 23.7 mW and 0.017 mm 2 , respectively.

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Section: Resultsmentioning

confidence: 99%