Optimization of Signal Processing Applications Using Parameterized Error Models for Approximate Adders

Abstract

Approximate circuit design has gained significance in recent years targeting error-tolerant applications. In the literature, there have been several attempts at optimizing the number of approximate bits of each approximate adder in a system for a given accuracy constraint. For computational efficiency, the error models used in these routines are simple expressions obtained using regression or by assuming inputs or the error is uniformly distributed. In this article, we first demonstrate that for many approximate adders, these assumptions lead to an inaccurate prediction of error statistics for multi-level circuits. We show that mean error and mean square error can be computed accurately if static probabilities of adders at all stages are taken into account. Therefore, in a system with a certain type of approximate adder, any optimization framework needs to take into account not just the functionality of the adder but also its position in the circuit, functionality of its parents, and the number of approximate bits in the parent blocks. We propose a method to derive parameterized error models for various types of approximate adders. We incorporate these models within an optimization framework and demonstrate that the noise power is computed accurately.

Analysis of power–accuracy trade‐off in digital signal processing applications using low‐power approximate adders

“…We compute the mean and MSE of each approximate adder using parameterized error models detailed in Ref. [13]. An optimization framework discussed in Ref.…”

“…An optimization framework discussed in Ref. [13] is used to fix the number of approximate bits in each adder for a given accuracy constraint. We first obtain the optimum number of approximate bits for each adder in the system, for a given MSE using the optimization framework.…”

“…In order to compare power savings and compression in DCT across adders, we used the optimizer [13] to find the optimal number of approximate bits of each adder in the DCT block for a given PSNR. This enables us to identify three different PSNR regimes for DCT with corresponding clear guidelines for the choice of adder in each regime, which we have not seen in any previous work.…”

“…Systems contain multiple adders, and in order to do a fair comparison, we need to find the optimal set of approximate bits for each adder such that the system specification is met. For this purpose, we have used an optimizer developed by us [13]. Once the optimal number of bits that can be approximated is known, it is possible to compare the potential power savings due to each type of adder.…”

Design and evaluation of ultra‐fast 8‐bit approximate multipliers using novel multicolumn inexact compressors

“…7 Therefore, several parameters of the circuits related to hardware-level approximation, which mainly targets arithmetic units, 8 can be improved by acceptable accuracy degradation. Image and signal processing have been among the fruitful areas for the employment of imprecise arithmetic circuits such as adders [9][10][11][12] and multipliers. [12][13][14][15][16][17][18][19][20][21] A multiplier is an arithmetic unit with a considerable impact on the performance of the entire system.…”