Analysis of power–accuracy trade‐off in digital signal processing applications using low‐power approximate adders

Dharmaraj, Celia; Vasudevan, V.; Chandrachoodan, Nitin

doi:10.1049/cdt2.12006

Cited by 3 publications

(2 citation statements)

References 25 publications

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“…Furthermore, the addition is applied to implement most of the other math operations, such as subtraction, multiplication, addressing etc. [2]. The speed and accuracy of an operator in a digital system mainly depend on its adders' performance [3].…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of a novel fast adder using logical effort method

tavakolaee

Ardeshir

Baleghi

2023

IET Computers & Digital Tech

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Addition, as one of the fundamental math operations, is applied widely in Very‐large‐scale integration systems and digital signal processing, such that the computational speed of a system depends mainly on the computational speed of its adders. There are various types of digital adders based on different methods. A novel adder is proposed which performs addition based on a path with a fewer number of levels, and, hence, with higher computational speed and lower power consumption. The goal and innovation is to design a structured fast adder that has a block that can be expanded to higher bits, and in this design, the calculation speed and power consumption of the proposed circuit are optimal. Each proposed adder circuit has several levels, and the formulae of each level are stated. Each level of the circuit is designed with a number of multiplexers and OR gates. The performance of the proposed adder has been investigated and evaluated in two parts of mathematical calculations and simulation, and it has also been compared with other existing fast adders, such as ripple carry adder, carry skip adder, carry select adder, carry look ahead adder and prefix kogge‐stone in cases of 8, 16, 32 and 64 bits. The results show that the proposed collector has a good performance compared to other adders‐based power consumption, power delay product and delay area product metrics.

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Section: Introductionmentioning

confidence: 99%

Design and analysis of a novel fast adder using logical effort method

tavakolaee

Ardeshir

Baleghi

2023

IET Computers & Digital Tech

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“…A universal strategic compressor‐based multiplier is described by Wang et al 18 In this work, shortcomings of previous approximate compressor‐based multipliers are defeated by the proposed method with acceptable error, and the overhead area is reduced. Dharmaraj et al 19 recommended the low‐power approximate adders and multipliers, which are accepted in digital signal processing applications.…”

Section: Introductionmentioning

confidence: 99%

An efficient VLSI architecture of 2‐D finite impulse response filter using enhanced approximate compressor circuits

Odugu

C²,

2021

Circuit Theory & Apps

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The very large‐scale integration (VLSI) design‐based architectures of 2‐D filters must have low power consumption and high speed rather than accuracy for image processing applications. The inexact computations reduce the delay, area, and power in arithmetic architectures, and utilizing this advantage an approximation can be introduced in 2‐D digital filters. In this work, circular symmetry is adopted to optimize the 2‐D finite impulse response (FIR) filter architecture, and it is implemented using imprecise multipliers and approximate compressors with acceptable accuracy. The exact 4:2 compressor is modified into an approximate 4:2 compressor by ignoring few inputs. Hence, hardware requirement and delay parameters are improved. The proposed compressor is designed by mixed logic rather than complete complementary metal‐oxide semiconductor (CMOS) logic. The dual value logic (DVL), transmission gate logic (TGL), and CMOS mixed logic gates are used to decrease the number of transistors in the circuits. The proposed compressors are used in the approximate Dadda multiplier (ADM). The ADMs are utilized to implement the 2‐D FIR filter architecture. The designed filter is coded in Verilog and implemented using field programmable gate array (FPGA). The hardware utilization is analyzed and compared with exact 2‐D FIR filters. Next, the proposed architecture is synthesized using Cadence genus tools, and physical design is carried out by Cadence Innovus tools in 45‐nm CMOS technology. The final physical design layout‐area, power, and delay reports are correlated with existing state‐of‐artworks. It is found that the proposed 2‐D FIR filter outperforms the existing works.

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Analysis of International Trade Relations Forecasting Model Based on Digital Trade

Ruan

2023

Lecture Notes on Data Engineering and Communications Technologies

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Analysis of power–accuracy trade‐off in digital signal processing applications using low‐power approximate adders

Cited by 3 publications

References 25 publications

Design and analysis of a novel fast adder using logical effort method

Design and analysis of a novel fast adder using logical effort method

An efficient VLSI architecture of 2‐D finite impulse response filter using enhanced approximate compressor circuits

Analysis of International Trade Relations Forecasting Model Based on Digital Trade

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