Approximate circuit design has gained significance in recent years targeting error-tolerant applications. In the literature, there have been several attempts at optimizing the number of approximate bits of each approximate adder in a system for a given accuracy constraint. For computational efficiency, the error models used in these routines are simple expressions obtained using regression or by assuming inputs or the error is uniformly distributed. In this article, we first demonstrate that for many approximate adders, these assumptions lead to an inaccurate prediction of error statistics for multi-level circuits. We show that mean error and mean square error can be computed accurately if static probabilities of adders at all stages are taken into account. Therefore, in a system with a certain type of approximate adder, any optimization framework needs to take into account not just the functionality of the adder but also its position in the circuit, functionality of its parents, and the number of approximate bits in the parent blocks. We propose a method to derive parameterized error models for various types of approximate adders. We incorporate these models within an optimization framework and demonstrate that the noise power is computed accurately.
Approximate circuit design has gained significance in recent years targeting error tolerant applications. In this paper, we consider the problem of minimizing the power for a given accuracy, in a signal processing application with accurate adders replaced by low-power approximate adders. We first demonstrate that the commonly used assumption that the inputs to the adder are uniformly distributed results in an inaccurate prediction of error statistics for multi-level circuits. To overcome this problem, we propose the use of parameterized error models for adders, with input static probabilities as parameters. The static probability computation in our work considers not just the functionality of the adder but also its position in the circuit, functionality of its parents and the number of approximate bits in the parent blocks. This parameterized error model can be incorporated in any optimization framework. We demonstrate up to 6.5 dB improvement in the accuracy of noise power prediction when the proposed model is used to optimize an 8 × 8 DCT.
In recent years, approximate circuit design targeting the error‐tolerant applications has gained significance. In this study, the authors propose a metric that ranks a stand‐alone approximate adder in terms of power savings obtained for a given mean error distance/mean square error (MSE). The authors demonstrate that this ranking of approximate adders can be used in applications that contain adder trees and registers. In applications that also have accurate multipliers interspersed with adders, the authors find that certain types of approximations in the adders result in more power‐efficient implementations of multipliers. Besides power savings, the other metrics of interest are noise floor and mean error in filtering applications and the compression achieved for a given peak signal‐to‐noise ratio (PSNR) in image compression applications. The authors also show that for the same overall MSE, there is a trade‐off between noise floor and mean error. This makes it possible to classify these adders based on whether they result in an increased noise floor or a mean error for the same overall MSE. Furthermore, the authors discuss the effect of using an approximate discrete cosine transform block to meet the reduced PSNR requirements, on the overall compression levels and the trade‐offs involved in the process.
Approximate circuit design has gained significance in recent years targeting error tolerant applications. In this paper, we consider the problem of minimizing the power for a given accuracy, in a signal processing application with accurate adders replaced by low-power approximate adders. We first demonstrate that the commonly used assumption that the inputs to the adder are uniformly distributed results in an inaccurate prediction of error statistics for multi-level circuits. To overcome this problem, we propose the use of parameterized error models for adders, with input static probabilities as parameters. The static probability computation in our work considers not just the functionality of the adder but also its position in the circuit, functionality of its parents and the number of approximate bits in the parent blocks. This parameterized error model can be incorporated in any optimization framework. We demonstrate up to 6.5 dB improvement in the accuracy of noise power prediction when the proposed model is used to optimize an 8 × 8 DCT.
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