Low-power and variation-aware approximate arithmetic units for Image Processing Applications

Mirzaei, Mohammad; Mohammadi, Siamak

doi:10.1016/j.aeue.2021.153825

Cited by 15 publications

(5 citation statements)

References 31 publications

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“…The structure can be adapted both for carry propagation adders and parallel-prefix adders. The authors of [39] proposed three schematic models of approximate adders with a modified structure. The developments implementation has reduced power and time costs with a moderate number of computational errors.…”

Section: B Processing Elements Modificationmentioning

confidence: 99%

Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

Nagornov,

Lyakhov,

Bergerman

et al. 2024

IEEE Access

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The technology development greatly increases the amount of digital visual information. Existing devices cannot efficiently process such huge amounts of data. The technical characteristics of digital image processing (DIP) devices and systems are being actively improved to resolve this contradiction in science and technology. The state-of-the-art methodology includes a huge number of very diverse approaches at the mathematical, software, and hardware implementation levels. We have analyzed all modern trends to improve the technical characteristics of DIP devices and systems. The main distinguishing feature of this review is that we are not limited to considering various aspects of neural network image processing, to which the vast majority of both review and research papers on the designated topic are devoted. Review papers on the subject under consideration are analyzed. Various mathematical and arithmetic-logical methods for improving the characteristics of image processing devices are described in detail. Original and significant architectural and structural solutions are analyzed. Promising neural network models of visual data processing are characterized. Hardware platforms for the design and operation of DIP systems that are efficient in terms of resource costs are considered. The most significant improvements achieved through the hardware implementation of models and methods on field-programmable gate arrays and application-specific integrated circuits are noted.INDEX TERMS High-performance computing, low-area design, low-power device, energy-efficient architecture, neural network, hardware accelerator, FPGA, ASIC.

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Section: B Processing Elements Modificationmentioning

confidence: 99%

Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

Nagornov,

Lyakhov,

Bergerman

et al. 2024

IEEE Access

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“…To balance the hardware criteria and application level, the different FoMs are established to involve both circuit and accuracy parameters, like FoM 1 , which is calculated by (25).…”

Section: The Fom Assessmentsmentioning

confidence: 99%

“…Also, the AFA1 has an inverter in the C out , which provides high power consumption with low driving ability. Also in Mirzaei and Mohammadi, 25 a similar procedure has been used and three other circuits named AFA4, AFA5, and AFA6 by 17, 6, and 19 transistors, respectively, were presented, and in the order produced 2, 4, and 2 errors. Although compared with AFA1 to AFA3, this design has a suitable trade‐off between error and area, but with the direct paths between V DD and GND and using extra inverters, these circuits also suffer from high power and low drivability.…”

Section: Previous Fas and Compressorsmentioning

confidence: 99%

A high‐efficient imprecise discrete cosine transform block based on a novel full adder and Wallace multiplier for bioimages compression

Esmaeili

Pesaran

Shiri

2023

Circuit Theory & Apps

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Sophisticated systems take advantage of approximate circuits for energy management. A gate-level structure is introduced to make a novel imprecise full adder (FA) cell by the gate diffusion input (GDI) strategy. The carbon nanotube field-effect transistor (CNTFET) technology lowers the FA power, and the swing issue is resolved by the dynamic threshold (DT) technique. The FA specifications are 10 transistors, two internal nodes, 0.191-μm 2 area, three errors, and an error rate (ER) of 37.5%. Some inputs are directly passed to the final stage of the FA to reduce the delay and dynamic power. The FA is used in three 4:2 compressors with 12, 16, and 20 transistors, respectively. The compressors are based on the modified stacking concept to attain low power, small area, and high speed. The compressors are used up in the partial product reduction tree (PPRT) of a new 8-bit inexact multiplier. Regarding the multiplier, the power-delay product (PDP) is decreased by 25.21%, and the normalized mean error distance (NMED) shows high accuracy. An imprecise discrete cosine transform (DCT) is implemented by the multiplier for image compression, and compared with the literature, the peak signal-to-noise ratio (PSNR) and structural similarity index metric (SSIM) are amended by 8.26% and 7.29%, respectively.

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“…By increasing the number of the erroneous results in 1-bit full adder’s truth table, the complexity of the designs decreases; based on this, three different 1-bit approximate full adders are proposed [ 32 ]. In [ 19 , 50 ], at the transistor level, approximate 1-bit adders are derived from the conventional mirror adders and XOR/XNOR-based adders by removing transistors and/or replacing some parts of the adders with a small circuitry; then, a generic approximate adder is implemented using approximate 1-bit adders.…”

Section: Introductionmentioning

confidence: 99%

Energy-Efficient Hardware Implementation of Fully Connected Artificial Neural Networks Using Approximate Arithmetic Blocks

Nojehdeh

Altun

2023

Circuits Syst Signal Process

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In this paper, we explore efficient hardware implementation of feedforward artificial neural networks (ANNs) using approximate adders and multipliers. Due to a large area requirement in a parallel architecture, the ANNs are implemented under the time-multiplexed architecture where computing resources are re-used in the multiply accumulate (MAC) blocks. The efficient hardware implementation of ANNs is realized by replacing the exact adders and multipliers in the MAC blocks by the approximate ones taking into account the hardware accuracy. Additionally, an algorithm to determine the approximate level of multipliers and adders due to the expected accuracy is proposed. As an application, the MNIST and SVHN databases are considered. To examine the efficiency of the proposed method, various architectures and structures of ANNs are realized. Experimental results show that the ANNs designed using the proposed approximate multiplier have a smaller area and consume less energy than those designed using previously proposed prominent approximate multipliers. It is also observed that the use of both approximate adders and multipliers yields, respectively, up to 50% and 10% reduction in energy consumption and area of the ANN design with a small deviation or better hardware accuracy when compared to the exact adders and multipliers.

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Low-power and variation-aware approximate arithmetic units for Image Processing Applications

Cited by 15 publications

References 31 publications

Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

Modern Trends in Improving the Technical Characteristics of Devices and Systems for Digital Image Processing

A high‐efficient imprecise discrete cosine transform block based on a novel full adder and Wallace multiplier for bioimages compression

Energy-Efficient Hardware Implementation of Fully Connected Artificial Neural Networks Using Approximate Arithmetic Blocks

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