Optimization of Layout and Doping Profile Design for BT(Body Tied)-FinFET DRAM

Abstract

In this paper, a device design guideline of sub 60nm BT-FinFET (Body Tied Fin FET) DRAM cell transistor is proposed. The V T controllability and variation were compared for 3 different implant concepts (blanket, local channel, and asymmetric S/D) and 2 different fin active designs (uneven and straight active type). Those were systemically analyzed for sub 60nm BT-FinFET device. And finally, the optimal structure for mass production is discussed.

Parasitic S/D resistance effects on hot-carrier reliability in body-tied FinFETs

“…The plot of W Fin = 20 nm without R ext was expected to be similar to W Fin = 100 nm with R ext = 5 kΩ corresponding to the total series resistance of W Fin = 20 nm, which was extracted by the ∆L method [10]. In the case of fully depleted thinbody FinFETs, the channel dopant could be easily diffused out and the threshold voltage (V T ) dropped as the W Fin reduces [11]. Due to the reduction of the space charge and the vertical electric field that must be supported by the gate bias at the expense of the inversion charge, the saturation voltage (V Dsat ) increased [12].…”