Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices

Abstract

Abstract-This paper presents a workgroup synthesis mechanism to compile an OpenCL kernel to FPGA-based accelerators embedded in a multi-core CPU system-on-a-chip (SoC). The OpenCL kernels considered in this paper exhibit regular data access patterns. Coping with the limited amount of internal memory in embedded FPGAs, the workgroup synthesis utilises a novel data access pattern formulation to describe the parallelism already provided by the OpenCL kernels. To provide an OpenCL framework prototype to validate the proposed technique, a source-to-source compiler that transforms the OpenCL kernel into C/C++ code is developed. Then vendor-specific high-level synthesis tools are used to convert the C/C++ code into the FPGA bitstream. Results based on popular real applications show up to 89.8% improvement in the execution time compared to the commercial FPGA OpenCL implementations.

Automated Bug Detection for High-level Synthesis of Multi-threaded Irregular Applications

“…Efforts on OpenCL are led by the main FPGA vendors Xilinx [49] and Intel [17]. Hosseinabady and Nunez-Yanez [25] have proposed improvement to the synthesis of OpenCL workgroups in hybrid ARM-FPGA devices. Owaida et al [39] have created a Finite State Machine with a Dat-aPath model suitable for execution of an OpenCL kernel, with a streaming unit to allow fast access to global data.…”

A Case for Work-stealing on FPGAs with OpenCL Atomics

“…Several authors have investigated the capabilities of Open-CL for FPGAs [6,14,16,10,17], but their focus has been on highly-uniform, FPGA-friendly benchmarks such as vector addition and matrix multiplication.…”