Reconfigurable Hardware Accelerator for Profile Hidden Markov Models

Ibrahim, Atef; Elsimary, Hamed; Aljumah, Abdullah; Gebali, Fayez

doi:10.1007/s13369-016-2162-y

Cited by 7 publications

(2 citation statements)

References 33 publications

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“…A nonlinear scheduling function was applied to the DG and a nonlinear projection function was used to implement a unified processor core to perform both modular multiplication and squaring operations. We followed a systematic approach previously reported by the authors of this paper in [30][31][32][33][34][35][36] to extract the processor core of one of the efficient multiplier and squaring algorithms previously reported in the literature, the bipartite multiplication and squaring algorithm suggested by Kim in [37]. We can briefly summarize the approach as follows:…”

Section: Contributionmentioning

confidence: 99%

Energy-Efficient Word-Serial Processor for Field Multiplication and Squaring Suitable for Lightweight Authentication Schemes in RFID-Based IoT Applications

Ibrahim

Gebali

2021

Applied Sciences

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Radio-Frequency Identification (RFID) technology is a crucial technology used in many IoT applications such as healthcare, asset tracking, logistics, supply chain management, assembly, manufacturing, and payment systems. Nonetheless, RFID-based IoT applications have many security and privacy issues restricting their use on a large scale. Many authors have proposed lightweight RFID authentication schemes based on Elliptic Curve Cryptography (ECC) with a low-cost implementation to solve these issues. Finite-field multiplication are at the heart of these schemes, and their implementation significantly affects the system’s overall performance. This article presents a formal methodology for developing a word-based serial-in/serial-out semisystolic processor that shares hardware resources for multiplication and squaring operations in GF(2n). The processor concurrently executes both operations and hence reduces the execution time. Furthermore, sharing the hardware resources provides savings in the area and consumed energy. The acquired implementation results for the field size n=409 indicate that the proposed structure achieves a significant reduction in the area–time product and consumed energy over the previously published designs by at least 32.3% and 70%, respectively. The achieved results make the proposed design more suitable to realize cryptographic primitives in resource-constrained RFID devices.

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Section: Contributionmentioning

confidence: 99%

Energy-Efficient Word-Serial Processor for Field Multiplication and Squaring Suitable for Lightweight Authentication Schemes in RFID-Based IoT Applications

Ibrahim

Gebali

2021

Applied Sciences

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“…In this paper, we propose a word-based two-dimensional SISO systolic processor for combined field multiplication and squaring over GF (2 m ). The main difference between the proposed SISO architecture and the other types of word-serial multiplier architecture is that the proposed multiplier-squarer structure is extracted by using a systematic approach [33][34][35][36][37][38][39]. In contrast, the other word-serial multiplier structures are extracted conventionally without the use of specific methodology.…”

Section: Paper Contributionmentioning

confidence: 99%

Word-Based Systolic Processor for Field Multiplication and Squaring Suitable for Cryptographic Processors in Resource-Constrained IoT Systems

Ibrahim

Gebali

2021

Electronics

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Internet of things (IoT) technology provides practical solutions for a wide range of applications, including but not limited to, smart homes, smart cities, intelligent grid, intelligent transportation, and healthcare. Security and privacy issues in IoT are considered significant challenges that prohibit its utilization in most of these applications, especially relative to healthcare applications. Cryptographic protocols should be applied at the different layers of IoT framework, especially edge devices, to solve all security concerns. Finite-field arithmetic, particularly field multiplication and squaring, represents the core of most cryptographic protocols and their implementation primarily affects protocol performance. In this paper, we present a compact and combined two-dimensional word-based serial-in/serial-out systolic processor for field multiplication and squaring over GF(2m). The proposed structure features design flexibility to manage hardware utilization, execution time, and consumed energy. Application Specific Integrated Circuit (ASIC) Implementation results of the proposed word-serial design and the competitive ones at different embedded word-sizes show that the proposed structure realizes considerable saving in the area and consumed energy, up to 93.7% and 98.2%, respectively. The obtained results enable the implementation of restricted cryptographic primitives in resource-constrained IoT edge devices such as wearable and implantable medical devices, smart cards, and wireless sensor nodes.

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FPGA-Based Hardware-Accelerated Design of Linear Prediction Analysis for Real-Time Speech Signal

Singh

Chandel

2023

Arab J Sci Eng

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Reconfigurable Hardware Accelerator for Profile Hidden Markov Models

Cited by 7 publications

References 33 publications

Energy-Efficient Word-Serial Processor for Field Multiplication and Squaring Suitable for Lightweight Authentication Schemes in RFID-Based IoT Applications

Energy-Efficient Word-Serial Processor for Field Multiplication and Squaring Suitable for Lightweight Authentication Schemes in RFID-Based IoT Applications

Word-Based Systolic Processor for Field Multiplication and Squaring Suitable for Cryptographic Processors in Resource-Constrained IoT Systems

FPGA-Based Hardware-Accelerated Design of Linear Prediction Analysis for Real-Time Speech Signal

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