Optimal memory configuration analysis in tri-hybrid solid-state drives with storage class memory and multi-level cell/triple-level cell NAND flash memory

Matsui, Chihiro; Yamada, Tomoaki; Sugiyama, Yusuke; Yamaga, Yusuke; Takeuchi, Ken

doi:10.7567/jjap.56.04ce02

Cited by 12 publications

(13 citation statements)

References 23 publications

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“…Most works classify the data or write operations as hot or cold depending on length of write requests or random/sequential nature 8,10,15,18,24,34,35,38,41,45,47,51 or access frequency 8,45 to store them to different memory cells. Most works classify the data or write operations as hot or cold depending on length of write requests or random/sequential nature 8,10,15,18,24,34,35,38,41,45,47,51 or access frequency 8,45 to store them to different memory cells.…”

Section: Key Ideas Of Different Techniquesmentioning

confidence: 99%

“…Several works discuss strategies to migrate data from SLC to MLC, 24,27,35,38,43,45,47,48 SLC to TLC, 28 MLC to TLC 24,40 or PCM to Flash 15,41,42 to utilize the space efficiently and improve performance. Several works discuss strategies to migrate data from SLC to MLC, 24,27,35,38,43,45,47,48 SLC to TLC, 28 MLC to TLC 24,40 or PCM to Flash 15,41,42 to utilize the space efficiently and improve performance.…”

Section: Key Ideas Of Different Techniquesmentioning

confidence: 99%

“…1. Most works classify the data or write operations as hot or cold depending on length of write requests or random/sequential nature 8,10,15,18,24,34,35,38,41,45,47,51 or access frequency 8,45 to store them to different memory cells. Also, pages belonging to metadata can be directly marked as hot.…”

Section: Key Ideas Of Different Techniquesmentioning

confidence: 99%

“…2. Several works discuss strategies to migrate data from SLC to MLC, 24,27,35,38,43,45,47,48 SLC to TLC, 28 MLC to TLC 24,40 or PCM to Flash 15,41,42 to utilize the space efficiently and improve performance.…”

Section: Key Ideas Of Different Techniquesmentioning

confidence: 99%

“…They study the impact of different NVRAM area cost models (viz, optimistic and pessimistic), NVRAM:Flash capacity ratio, NVRAM read:write latency ratio, etc, and also, study strategies for mapping hot/cold and sequential/random data to NVRAM or Flash. 16 Working of the technique of Matsui et al 24 (RAM refers to an SCM, eg, ReRAM) to SLC and MLC chips, respectively. Writing and updating of data in the registers is performed similar to previous techniques.…”

Section: Using Scms or Dram As A Buffermentioning

confidence: 99%

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A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

Alsalibi

Mittal

Al-Betar

et al. 2018

Concurrency and Computation

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Flash memory-based solid-state drives (SSDs) offer several attractive features and benefits compared to hard disk drive (HDD), such as shock resistance and better performance especially for random data access. Depending on the number of bits in each cell, Flash memory can be designed as single/multi/triple level cell (SLC/MLC/TLC), which have different performance, density, cost and write endurance characteristics. To bring the best of these together, several researchers have proposed designing SSD using hybrid SLC/MLC/TLC Flash memory. However, these SSDs also present several challenges such as buffer management, placement of hot/cold data in suitable portion, and intelligent garbage collection. Several recent techniques aim to address these challenges.In this paper, we present a survey of techniques for managing SSDs designed with SLC/MLC/TLC Flash memory. We classify the works on several axes to bring out their similarities and differences.We aim to synthesize the state-of-art progress in hybrid SSD management and also spark further research in this area. KEYWORDSflash translation layer, garbage collection, hybrid solid state disk, NAND flash memory, wear leveling INTRODUCTIONAs the amount of digital data continues to grow at an exponential rate and key applications become more data intensive, efficient storage architectures and management techniques have become more important than ever before. Conventionally, hard disk drive* has been used as a storage device; however, its limitations such as poor performance (especially for random accesses), higher form factor, and vulnerability to shocks and magnetic fields have encouraged researchers to explore its alternatives.Flash memory is a promising technology for designing storage devices due to its several attractive properties, eg, high performance and density, low power consumption, noise-free operation, and immunity to shocks and magnetic fields. 2-6 Also, its cost has been decreasing in recent years and it is expected to provide even better cost efficiency than HDD in near future. Based on the number of bits stored in each cell, Flash can be characterized as SLC (1 bit), MLC † (2 bit) and TLC (3 bits). As shown in Table 1, these cell types provide a spectrum of properties and trade-offs. Specifically, on going from SLC to MLC to TLC, the performance and write endurance decrease whereas density and cost efficiency improve.To achieve the best of these three cell types, hybrid SSD designs have been proposed, which use Flash memories of multiple cell types to improve performance, energy efficiency, and reliability. 16 However, these hybrid SSD designs also bring challenges, such as selection of relative proportion of SLC/MLC/TLC, efficient mapping/moving of hot/cold data to them, accounting for their disparate write endurance and density values, and

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Section: Key Ideas Of Different Techniquesmentioning

confidence: 99%

Section: Key Ideas Of Different Techniquesmentioning

confidence: 99%

Section: Key Ideas Of Different Techniquesmentioning

confidence: 99%

Section: Key Ideas Of Different Techniquesmentioning

confidence: 99%

Section: Using Scms or Dram As A Buffermentioning

confidence: 99%

See 3 more Smart Citations

A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

Alsalibi

Mittal

Al-Betar

et al. 2018

Concurrency and Computation

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Optimized Method for Low‐Energy and Highly Reliable Multibit Operation in a HfO₂‐Based Resistive Switching Device

Ryu

Park

Chung

et al. 2018

Adv Elect Materials

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Four‐Bits‐Per‐Cell Operation in an HfO₂‐Based Resistive Switching Device

Kim

Yang

et al. 2017

Small

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The quadruple-level cell technology is demonstrated in an Au/Al O /HfO /TiN resistance switching memory device using the industry-standard incremental step pulse programming (ISPP) and error checking/correction (ECC) methods. With the highly optimistic properties of the tested device, such as self-compliance and gradual set-switching behaviors, the device shows 6σ reliability up to 16 states with a state current gap value of 400 nA for the total allowable programmed current range from 2 to 11 µA. It is demonstrated that the conventional ISPP/ECC can be applied to such resistance switching memory, which may greatly contribute to the commercialization of the device, especially competitively with NAND flash. A relatively minor improvement in the material and circuitry may enable even a five-bits-per-cell technology, which can hardly be imagined in NAND flash, whose state-of-the-art multiple-cell technology is only at three-level (eight states) to this day.

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Optimal memory configuration analysis in tri-hybrid solid-state drives with storage class memory and multi-level cell/triple-level cell NAND flash memory

Cited by 12 publications

References 23 publications

A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

Optimized Method for Low‐Energy and Highly Reliable Multibit Operation in a HfO₂‐Based Resistive Switching Device

Four‐Bits‐Per‐Cell Operation in an HfO₂‐Based Resistive Switching Device

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Optimal memory configuration analysis in tri-hybrid solid-state drives with storage class memory and multi-level cell/triple-level cell NAND flash memory

Cited by 12 publications

References 23 publications

A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

Optimized Method for Low‐Energy and Highly Reliable Multibit Operation in a HfO2‐Based Resistive Switching Device

Four‐Bits‐Per‐Cell Operation in an HfO2‐Based Resistive Switching Device

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Product

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Optimized Method for Low‐Energy and Highly Reliable Multibit Operation in a HfO₂‐Based Resistive Switching Device

Four‐Bits‐Per‐Cell Operation in an HfO₂‐Based Resistive Switching Device