A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

Alsalibi, Ahmed Izzat; Mittal, Sparsh; Al-Betar, Mohammed Azmi; Sumari, Putra

doi:10.1002/cpe.4420

Cited by 24 publications

(8 citation statements)

References 48 publications

(242 reference statements)

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“…We classify the works based on key parameters to highlight their similarities and differences. We believe that the techniques reviewed here will also be useful for current and future lifetime-limited or write-agnostic memories such as Flash memory [42]. We conclude this paper with a brief mention of future research challenges.…”

Section: Conclusion and Future Outlookmentioning

confidence: 94%

A Survey of Techniques for Improving Security of Non-volatile Memories

Mittal

Alsalibi²

2018

J Hardw Syst Secur

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Due to their high-density and near-zero leakage power consumption, non-volatile memories (NVMs) are promising candidates for designing future memory systems. However, compared to conventional memories, NVMs also face more severe security threats, e.g., the limited write endurance of NVMs makes them vulnerable to write attacks. Also, the nonvolatility of NVMs allows the data to persist even after power-off, which can be accessed by a malicious agent. Further, encryption endangers NVM lifetime and performance by reducing the efficacy of redundant write avoidance techniques. In this paper, we present a survey of techniques for improving security of NVM-based memories by addressing the aforementioned challenges. We highlight the key ideas of the techniques along with their similarities and differences. This paper is expected to be useful for researchers and practitioners in the area of memory and system security.

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Section: Conclusion and Future Outlookmentioning

confidence: 94%

A Survey of Techniques for Improving Security of Non-volatile Memories

Mittal

Alsalibi²

2018

J Hardw Syst Secur

Self Cite

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“…Three-dimensional structure technology [ 2 ] is committed to transforming a planar structure into a three-dimensional structure, which increases the storage capacity under the same area. Multi-bit memory cell technology [ 3 ] focuses on improving the number of bits in the storage unit in order to achieve a multiple increase in storage capacity. With gradual in-depth study of the two technologies, researchers have found that while the storage density of NAND flash memory has doubled, the data reliability problem has worsened.…”

Section: Introductionmentioning

confidence: 99%

An SVM-Based NAND Flash Endurance Prediction Method

Zhang

Wang²,

Zhuo

et al. 2021

Micromachines

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NAND flash memory is widely used in communications, commercial servers, and cloud storage devices with a series of advantages such as high density, low cost, high speed, anti-magnetic, and anti-vibration. However, the reliability is increasingly getting worse while process improvements and technological advancements have brought higher storage densities to NAND flash memory. The degradation of reliability not only reduces the lifetime of the NAND flash memory but also causes the devices to be replaced prematurely based on the nominal value far below the minimum actual value, resulting in a great waste of lifetime. Using machine learning algorithms to accurately predict endurance levels can optimize wear-leveling strategies and warn bad memory blocks, which is of great significance for effectively extending the lifetime of NAND flash memory devices and avoiding serious losses caused by sudden failures. In this work, a multi-class endurance prediction scheme based on the SVM algorithm is proposed, which can predict the remaining P-E cycle level and the raw bit error level after various P-E cycles. Feature analysis based on endurance data is used to determine the basic elements of the model. Based on the error features, we present a variety of targeted optimization strategies, such as extracting the numerical features closely related to the endurance, and reducing the noise interference of transient faults through short-term repeated operations. Besides a high-parallel flash test platform supporting multiple protocols, a feature preprocessing module is constructed based on the ZYNQ-7030 chip. The pipelined module of SVM decision model can complete a single prediction within 37 us.

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“…However, many data classification and allocation techniques for hybrid SSDs are not suitable for the access characteristics of an LSMKV. Many previous techniques have classified data that are frequently written to the same logical address as hot data and allocate them to fast storage spaces [1], [7]- [9], [13], [18], [20], [22]. LSMKVs write key-value data to adjacent logical addresses even if the write operation is an update to the key-value data in the storage [10], [16].…”

Section: Introductionmentioning

confidence: 99%

Level Aware Data Placement Technique for Hybrid NAND Flash Storage of Log-Structured Merge-Tree Based Key-Value Store System

et al. 2020

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A log-structured merge-tree-based key value store (LSMKV) is an append-only database for storing and retrieving unstructured data, especially in a write-intensive environment. This database uses hierarchical components to store and manage data. Upper-level components have a shorter data lifespan and a higher access locality than lower-level components. Hence, the data access latency of the upper-level components significantly affects the performance of the entire database. Hybrid solid-state drives (SSD) composed of media with different access speeds can improve the performance of an LSMKV by storing the upper-level components using a fast storage space. However, many hybrid SSDs use fast storage spaces to store data that are frequently allocated to the same logical address; they are not suitable for storing appendonly component data, which are allocated to adjacent logical addresses. This paper proposes a hybrid SSDmanagement method to reduce the data access latency of append-only LSMKVs and increase the durability of hybrid SSDs. The proposed method allocates the data of upper-level components to a fast storage space using the level information of the data as a hint. This study utilizes dynamic data separation to determine the components to be placed in the fast storage space, NAND block management to store the data with similar lifespans in the same fast NAND block, and a data-relocation method to migrate long-lived data from the fast NAND region to another NAND region. Experimental results indicate that the proposed method reduces the average I/O latency by an average of 12% and increases the device durability by an average of 22%.

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A survey of techniques for architecting SLC/MLC/TLC hybrid Flash memory–based SSDs

Cited by 24 publications

References 48 publications

A Survey of Techniques for Improving Security of Non-volatile Memories

A Survey of Techniques for Improving Security of Non-volatile Memories

An SVM-Based NAND Flash Endurance Prediction Method

Level Aware Data Placement Technique for Hybrid NAND Flash Storage of Log-Structured Merge-Tree Based Key-Value Store System

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