OpenSoC Fabric: On-chip network generator

Fatollahi-Fard, Farzad; Donofrio, David; Shalf, John

doi:10.1109/ispass.2016.7482094

Cited by 22 publications

(16 citation statements)

References 20 publications

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“…The OpenSoC Fabric [4] is an open-source NoC generator written in Chisel. It is intended to provide a system-on-chip for large-scale design exploration.…”

Section: Related Workmentioning

confidence: 99%

“…The PaterNoster NI is relatively large, as it contains a fully associative receive buffer to be able to read from any channel independently of the receiving order. The table also presents the results for a single router of the OpenSoC NoC [4]. For this result, we generated the Verilog code for the default configuration, which is a 2 × 2 mesh with routing based on virtual channels and one local port.…”

Section: Hardware Costmentioning

confidence: 99%

“…NIs can be optimized for quite different uses. We identify five different uses of NoCs: (1) supporting cache coherence protocols, (2) single word memory accesses to a different core or input/output device, (3) access to a shared external memory, (4) supporting message passing between cores, and (5) supporting streaming data. Depending on the types of traffic supported, the NoCs and in particular the NIs providing the interface to the NoC may be rather diverse.…”

Section: Introductionmentioning

confidence: 99%

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A Minimal Network Interface for a Simple Network-on-Chip

Schoeberl

Pezzarossa

Sparsø

2019

Architecture of Computing Systems – ARCS 2019

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“…The OpenSoC Fabric [4] is an open-source NoC generator written in Chisel. It is intended to provide a system-on-chip for large-scale design exploration.…”

Section: Related Workmentioning

confidence: 99%

Section: Hardware Costmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Minimal Network Interface for a Simple Network-on-Chip

Schoeberl

Pezzarossa

Sparsø

2019

Architecture of Computing Systems – ARCS 2019

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“…These languages offer additional functionalities coming with functional-and object-oriented programming paradigms. Chisel has been successfully used to implement Rocket Chip [1] generator for RISC-V ISA processor tiles and OpenSoC Fabric [9] that allows generating parameterizable on-chip networks. However, no coherent cache memory subsystem generator has been implemented yet.…”

Section: Hardware Emulationmentioning

confidence: 99%

Open2C

Butko

Chen

Donofrio

et al. 2018

Proceedings of the International Symposium on Memory Systems

Self Cite

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A cache-coherent memory subsystem plays an important role in complex digital computing systems. It maintains memory consistency across on-chip caches that hide the memory latency to improve computational performance. Being managed by hardware, the cache subsystem facilitates multi-core system programming and allows developers to focus on other crucial aspects. However, due to extensive protocol-related traffic and lack of explicit data movement management, cache memory scalability becomes a big concern. Existing evaluation techniques, such as cycle-approximate estimation or cycle-accurate simulation, do not guarantee accurate and fast results in the first case or require tremendous amount of efforts to implement and modify the system in the second. We present Open Cache Coherence (Open2C). The project aims to provide a powerful yet flexible and easy-to-extend tool that enables exploring coherent cache memory subsystem for upcoming large-scale computing systems. Open2C includes a library of basic parameterized components that are required to build a complex coherent cache memory subsystem, such as miss register, TAG array, replacement policy unit, etc. The Open2C generator is written in Chisel language that allows each component to be accessed through provided methods in a functional and modular way. The generated system can be simulated using existing Chisel-based simulation tools or be compiled into the RTL and placed on FPGA for further evaluation. Open2C reduces the amount of effort researches spend on system implementation-allowing them to focus on the protocol itself or a separate unit optimization. CCS CONCEPTS • Computer systems organization → Architectures; • Computing methodologies → Modeling and simulation; • Hardware ACM acknowledges that this contribution was authored or co-authored by an employee, contractor, or affiliate of the United States government. As such, the United States government retains a nonexclusive, royalty-free right to publish or reproduce this article, or to allow others to do so, for government purposes only.

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“…Networks-on-chip (NoC) play a critical role in the integration of components in large-scale systems-on-chip (SoC) at design time, and have a major impact on their performance at run time. Over the last few years, the research community has produced many different frameworks and tools for NoC design and optimization [7,14,16,17]. Most of these approaches provide some degree of parameterization which allows designers to optimize the NoC architecture for the target SoC and the given ASIC or FPGA technology.…”

Section: Introductionmentioning

confidence: 99%

System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip

Yoon

Mantovani

Carloni

2017

Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip

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The network-on-Chip (NoC) is a critical subsystem for many largescale systems-on-chip (SoC). We present a complete framework for the design and optimization of NoCs at the system-level. By combining a library of pre-designed con gurable NoC modules specied in SystemC with high-level synthesis, we can generate a variety of alternative 2D-Mesh NoC architectures for a given SoC. We also support the automatic synthesis of network interfaces to translate between IP-speci c messages and NoC its. We demonstrate our approach with the design-space exploration of two complete SoCs running complex applications on a high-end FPGA board. CCS CONCEPTS • Networks → Network on chip; Network components; • Hardware → Network on chip;

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OpenSoC Fabric: On-chip network generator

Cited by 22 publications

References 20 publications

A Minimal Network Interface for a Simple Network-on-Chip

A Minimal Network Interface for a Simple Network-on-Chip

Open2C

System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip

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